Commit 32953485 authored by Aric Cyr's avatar Aric Cyr Committed by Alex Deucher
Browse files

drm/amd/display: Do not update DRR while BW optimizations pending 



[why]
While bandwidth optimizations are pending, it's possible a pstate change
will occur.  During this time, VSYNC handler should not also try to update
DRR parameters causing pstate hang

[how]
Do not adjust DRR if optimize bandwidth is set.

Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAric Cyr <aric.cyr@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 82a10aff

drivers/gpu/drm/amd/display/dc/core/dc.c

+29 −19
Original line number Diff line number Diff line
@@ -400,6 +400,13 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, 
{

	int i;



	/*

	 * Don't adjust DRR while there's bandwidth optimizations pending to

	 * avoid conflicting with firmware updates.

	 */

	if (dc->optimized_required || dc->wm_optimized_required)

		return false;



	stream->adjust.v_total_max = adjust->v_total_max;

	stream->adjust.v_total_mid = adjust->v_total_mid;

	stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
@@ -2180,10 +2187,15 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) 


	post_surface_trace(dc);



	if (dc->ctx->dce_version >= DCE_VERSION_MAX)

		TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);

	else

	/*

	 * Only relevant for DCN behavior where we can guarantee the optimization

	 * is safe to apply - retain the legacy behavior for DCE.

	 */



	if (dc->ctx->dce_version < DCE_VERSION_MAX)

		TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);

	else {

		TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);



		if (is_flip_pending_in_pipes(dc, context))

			return;
@@ -2201,6 +2213,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) 


		if (dc->debug.enable_double_buffered_dsc_pg_support)

			dc->hwss.update_dsc_pg(dc, context, true);

	}



	dc->optimized_required = false;

	dc->wm_optimized_required = false;
@@ -4169,12 +4182,9 @@ void dc_commit_updates_for_stream(struct dc *dc, 
			if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)

				new_pipe->plane_state->force_full_update = true;

		}

	} else if (update_type == UPDATE_TYPE_FAST && dc_ctx->dce_version >= DCE_VERSION_MAX) {

	} else if (update_type == UPDATE_TYPE_FAST) {

		/*

		 * Previous frame finished and HW is ready for optimization.

		 *

		 * Only relevant for DCN behavior where we can guarantee the optimization

		 * is safe to apply - retain the legacy behavior for DCE.

		 */

		dc_post_update_surfaces_to_stream(dc);

	}