Commit 32bc790a authored by Roy Luo's avatar Roy Luo Committed by Greg Kroah-Hartman
Browse files

dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 



Document the device tree bindings for the DWC3 USB controller found in
Google Tensor SoCs, starting with the G5 generation (codename: laguna).

The Tensor G5 silicon represents a complete architectural departure from
previous generations (like gs101), including entirely new clock/reset
schemes, top-level wrapper and register interface. Consequently,
existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating
this new device tree binding.

The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
Dual-Role Device single port with hibernation support.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: default avatarRoy Luo <royluo@google.com>
Link: https://patch.msgid.link/20251218-controller-v10-1-4047c9077274@google.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e715bc42

Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (c) 2025, Google LLC

%YAML 1.2

---

$id: http://devicetree.org/schemas/usb/google,lga-dwc3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Google Tensor Series G5 (Laguna) DWC3 USB SoC Controller



maintainers:

  - Roy Luo <royluo@google.com>



description:

  Describes the DWC3 USB controller block implemented on Google Tensor SoCs,

  starting with the G5 generation (laguna). Based on Synopsys DWC3 IP, the

  controller features Dual-Role Device single port with hibernation add-on.



properties:

  compatible:

    const: google,lga-dwc3



  reg:

    items:

      - description: Core DWC3 IP registers.



  interrupts:

    items:

      - description: Core DWC3 interrupt.

      - description: High speed power management event for remote wakeup.

      - description: Super speed power management event for remote wakeup.



  interrupt-names:

    items:

      - const: core

      - const: hs_pme

      - const: ss_pme



  clocks:

    items:

      - description: Non-sticky module clock.

      - description: Sticky module clock.



  clock-names:

    items:

      - const: non_sticky

      - const: sticky



  resets:

    items:

      - description: Non-sticky module reset.

      - description: Sticky module reset.

      - description: DRD bus reset.

      - description: Top-level reset.



  reset-names:

    items:

      - const: non_sticky

      - const: sticky

      - const: drd_bus

      - const: top



  power-domains:

    items:

      - description: Power switchable domain, the child of top domain.

          Turning it on puts the controller into full power state,

          turning it off puts the controller into power gated state.

      - description: Top domain, the parent of power switchable domain.

          Turning it on puts the controller into power gated state,

          turning it off completely shuts off the controller.



  power-domain-names:

    items:

      - const: psw

      - const: top



  iommus:

    maxItems: 1



  google,usb-cfg-csr:

    description:

      A phandle to a syscon node used to access the USB configuration

      registers. These registers are the top-level wrapper of the USB

      subsystem and provide control and status for the integrated USB

      controller and USB PHY.

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to the syscon node.

          - description: USB host controller configuration register offset.

          - description: USB custom interrrupts control register offset.



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - resets

  - reset-names

  - power-domains

  - power-domain-names

  - google,usb-cfg-csr



allOf:

  - $ref: snps,dwc3-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        usb@c400000 {

            compatible = "google,lga-dwc3";

            reg = <0 0x0c400000  0 0xd060>;

            interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,

                         <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,

                         <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;

            interrupt-names = "core", "hs_pme", "ss_pme";

            clocks = <&hsion_usbc_non_sticky_clk>,  <&hsion_usbc_sticky_clk>;

            clock-names = "non_sticky", "sticky";

            resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,

                     <&hsion_resets_usb_drd_bus>, <&hsion_resets_usb_top>;

            reset-names = "non_sticky", "sticky", "drd_bus", "top";

            power-domains = <&hsio_n_usb_psw>, <&hsio_n_usb>;

            power-domain-names = "psw", "top";

            phys = <&usb_phy 0>;

            phy-names = "usb2-phy";

            snps,quirk-frame-length-adjustment = <0x20>;

            snps,gfladj-refclk-lpm-sel-quirk;

            snps,incr-burst-type-adjustment = <4>;

            google,usb-cfg-csr = <&usb_cfg_csr 0x0 0x20>;

        };

    };

...

MAINTAINERS

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@@ -10722,6 +10722,7 @@ P: Documentation/process/maintainer-soc-clean-dts.rst 
C:	irc://irc.oftc.net/pixel6-kernel-dev

F:	Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

F:	Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml

F:	Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml

F:	arch/arm64/boot/dts/exynos/google/

F:	drivers/clk/samsung/clk-gs101.c

F:	drivers/soc/samsung/gs101-pmu.c