Commit 32cb1cc3 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
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drm/nouveau: add support for GB10x 



This commit enables basic support for the GB100/GB102 Blackwell GPUs.

Beyond HW class ID plumbing there's very little change here vs GH100.

Signed-off-by: default avatarBen Skeggs <bskeggs@nvidia.com>
Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
Reviewed-by: default avatarTimur Tabi <ttabi@nvidia.com>
Tested-by: default avatarTimur Tabi <ttabi@nvidia.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 862450a8

drivers/gpu/drm/nouveau/include/nvhw/ref/gb100/dev_hshub_base.h

0 → 100644
+28 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT

 *

 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.

 */

#ifndef __gb100_dev_hshub_base_h__

#define __gb100_dev_hshub_base_h__



#define NV_PFB_HSHUB0      0x00870fff:0x00870000



#define NV_PFB_HSHUB                                   0x00000FFF:0x00000000 /* RW--D */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO              0x00000E50 /* RW-4R */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR                31:0 /* RWIVF */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT     0x00000000 /* RWI-V */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK     0xFFFFFF00 /* ----V */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI              0x00000E54 /* RW-4R */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR                31:0 /* RWIVF */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT     0x00000000 /* RWI-V */

#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK     0x000FFFFF /* ----V */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO           0x000006C0 /* RW-4R */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR             31:0 /* RWIVF */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT  0x00000000 /* RWI-V */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK  0xFFFFFF00 /* ----V */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI           0x000006C4 /* RW-4R */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR             31:0 /* RWIVF */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT  0x00000000 /* RWI-V */

#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK  0x000FFFFF /* ----V */



#endif // __gb100_dev_hshub_base_h__

drivers/gpu/drm/nouveau/include/nvif/cl0080.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ struct nv_device_info_v0 { 
#define NV_DEVICE_INFO_V0_AMPERE                                           0x0d

#define NV_DEVICE_INFO_V0_ADA                                              0x0e

#define NV_DEVICE_INFO_V0_HOPPER                                           0x0f

#define NV_DEVICE_INFO_V0_BLACKWELL                                        0x10

	__u8  family;

	__u8  pad06[2];

	__u64 ram_size;

drivers/gpu/drm/nouveau/include/nvif/class.h

+9 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 


#define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040

#define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140

#define BLACKWELL_INLINE_TO_MEMORY_A                                 0x0000cd40



#define NV04_DISP                                     /* cl0046.h */ 0x00000046
@@ -87,6 +88,7 @@ 
#define AMPERE_CHANNEL_GPFIFO_A                       /* if0020.h */ 0x0000c56f

#define AMPERE_CHANNEL_GPFIFO_B                       /* if0020.h */ 0x0000c76f

#define HOPPER_CHANNEL_GPFIFO_A                                      0x0000c86f

#define BLACKWELL_CHANNEL_GPFIFO_A                                   0x0000c96f



#define NV50_DISP                                     /* if0010.h */ 0x00005070

#define G82_DISP                                      /* if0010.h */ 0x00008270
@@ -198,6 +200,8 @@ 


#define HOPPER_A                                                     0x0000cb97



#define BLACKWELL_A                                                  0x0000cd97



#define NV74_BSP                                                     0x000074b0



#define NVB8B0_VIDEO_DECODER                                         0x0000b8b0
@@ -205,6 +209,7 @@ 
#define NVC6B0_VIDEO_DECODER                                         0x0000c6b0

#define NVC7B0_VIDEO_DECODER                                         0x0000c7b0

#define NVC9B0_VIDEO_DECODER                                         0x0000c9b0

#define NVCDB0_VIDEO_DECODER                                         0x0000cdb0



#define GT212_MSVLD                                                  0x000085b1

#define IGT21A_MSVLD                                                 0x000086b1
@@ -234,6 +239,7 @@ 
#define AMPERE_DMA_COPY_A                                            0x0000c6b5

#define AMPERE_DMA_COPY_B                                            0x0000c7b5

#define HOPPER_DMA_COPY_A                                            0x0000c8b5

#define BLACKWELL_DMA_COPY_A                                         0x0000c9b5



#define NVC4B7_VIDEO_ENCODER                                         0x0000c4b7

#define NVC7B7_VIDEO_ENCODER                                         0x0000c7b7
@@ -257,15 +263,18 @@ 
#define AMPERE_COMPUTE_B                                             0x0000c7c0

#define ADA_COMPUTE_A                                                0x0000c9c0

#define HOPPER_COMPUTE_A                                             0x0000cbc0

#define BLACKWELL_COMPUTE_A                                          0x0000cdc0



#define NV74_CIPHER                                                  0x000074c1



#define NVB8D1_VIDEO_NVJPG                                           0x0000b8d1

#define NVC4D1_VIDEO_NVJPG                                           0x0000c4d1

#define NVC9D1_VIDEO_NVJPG                                           0x0000c9d1

#define NVCDD1_VIDEO_NVJPG                                           0x0000cdd1



#define NVB8FA_VIDEO_OFA                                             0x0000b8fa

#define NVC6FA_VIDEO_OFA                                             0x0000c6fa

#define NVC7FA_VIDEO_OFA                                             0x0000c7fa

#define NVC9FA_VIDEO_OFA                                             0x0000c9fa

#define NVCDFA_VIDEO_OFA                                             0x0000cdfa

#endif

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ struct nvkm_device { 
		GA100    = 0x170,

		GH100    = 0x180,

		AD100    = 0x190,

		GB10x    = 0x1a0,

	} card_type;

	u32 chipset;

	u8  chiprev;

drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ int tu102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n 
int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);

int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);

int gh100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);

int gb100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);



#include <subdev/bios.h>

#include <subdev/bios/ramcfg.h>