Unverified Commit 32d5f7ad authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "RISC-V: hwprobe: Misaligned scalar perf fix and rename" 

Evan Green <evan@rivosinc.com> says:

The CPUPERF0 hwprobe key was documented and identified in code as
a bitmask value, but its contents were an enum. This produced
incorrect behavior in conjunction with the WHICH_CPUS hwprobe flag.
The first patch in this series fixes the bitmask/enum problem by
creating a new hwprobe key that returns the same data, but is
properly described as a value instead of a bitmask. The second patch
renames the value definitions in preparation for adding vector misaligned
access info. As of this version, the old defines are kept in place to
maintain source compatibility with older userspace programs.

* b4-shazam-merge:
  RISC-V: hwprobe: Add SCALAR to misaligned perf defines
  RISC-V: hwprobe: Add MISALIGNED_PERF key

Link: https://lore.kernel.org/r/20240809214444.3257596-1-evan@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents e01d48c6 1f528887

Documentation/arch/riscv/hwprobe.rst

+22 −14
Original line number Diff line number Diff line
@@ -239,25 +239,33 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned

    accesses is unknown.

* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing

  the performance of misaligned scalar native word accesses on the selected set

  of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are

    emulated via software, either in or below the kernel.  These accesses are

    always extremely slow.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of

    misaligned scalar accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower

    than equivalent byte accesses.  Misaligned accesses may be supported

    directly in hardware, or trapped and emulated by software.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar

    accesses are emulated via software, either in or below the kernel.  These

    accesses are always extremely slow.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster

    than equivalent byte accesses.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native

    word sized accesses are slower than the equivalent quantity of byte

    accesses. Misaligned accesses may be supported directly in hardware, or

    trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are

    not supported at all and will generate a misaligned address fault.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native

    word sized accesses are faster than the equivalent quantity of byte

    accesses.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar

    accesses are not supported at all and will generate a misaligned address

    fault.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicboz block in bytes.

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 8

#define RISCV_HWPROBE_MAX_KEY 9



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{

arch/riscv/include/uapi/asm/hwprobe.h

+6 −0
Original line number Diff line number Diff line
@@ -82,6 +82,12 @@ struct riscv_hwprobe { 
#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE	6

#define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS	7

#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ	8

#define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF	9

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN		0

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED	1

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW		2

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_FAST		3

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED	4

/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */



/* Flags */

arch/riscv/kernel/sys_hwprobe.c

+6 −5
Original line number Diff line number Diff line
@@ -178,13 +178,13 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) 
			perf = this_perf;



		if (perf != this_perf) {

			perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN;

			perf = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;

			break;

		}

	}



	if (perf == -1ULL)

		return RISCV_HWPROBE_MISALIGNED_UNKNOWN;

		return RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;



	return perf;

}
@@ -192,12 +192,12 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) 
static u64 hwprobe_misaligned(const struct cpumask *cpus)

{

	if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS))

		return RISCV_HWPROBE_MISALIGNED_FAST;

		return RISCV_HWPROBE_MISALIGNED_SCALAR_FAST;



	if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available())

		return RISCV_HWPROBE_MISALIGNED_EMULATED;

		return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;



	return RISCV_HWPROBE_MISALIGNED_SLOW;

	return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;

}

#endif
@@ -225,6 +225,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, 
		break;



	case RISCV_HWPROBE_KEY_CPUPERF_0:

	case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:

		pair->value = hwprobe_misaligned(cpus);

		break;

arch/riscv/kernel/traps_misaligned.c

+3 −3
Original line number Diff line number Diff line
@@ -338,7 +338,7 @@ int handle_misaligned_load(struct pt_regs *regs) 
	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);



#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS

	*this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED;

	*this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;

#endif



	if (!unaligned_enabled)
@@ -532,13 +532,13 @@ static bool check_unaligned_access_emulated(int cpu) 
	unsigned long tmp_var, tmp_val;

	bool misaligned_emu_detected;



	*mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;

	*mas_ptr = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;



	__asm__ __volatile__ (

		"       "REG_L" %[tmp], 1(%[ptr])\n"

		: [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");



	misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);

	misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED);

	/*

	 * If unaligned_ctl is already set, this means that we detected that all

	 * CPUS uses emulated misaligned access at boot time. If that changed