Commit 32ef24e5 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Simplify uavflagprd_inv detection 



Instead of setting it on a gpu-per-gpu basis, converge it to the
intended "is A650 family or A7xx".

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660969/


Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 367380d2

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+6 −9
Original line number Diff line number Diff line
@@ -612,7 +612,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
		return PTR_ERR(gpu->common_ubwc_cfg);



	gpu->ubwc_config.rgb565_predicator = 0;

	gpu->ubwc_config.uavflagprd_inv = 0;

	gpu->ubwc_config.min_acc_len = 0;

	gpu->ubwc_config.ubwc_swizzle = 0x6;

	gpu->ubwc_config.macrotile_mode = 0;
@@ -634,15 +633,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
	if (adreno_is_a619_holi(gpu))

		gpu->ubwc_config.highest_bank_bit = 13;



	if (adreno_is_a621(gpu)) {

	if (adreno_is_a621(gpu))

		gpu->ubwc_config.highest_bank_bit = 13;

		gpu->ubwc_config.uavflagprd_inv = 2;

	}



	if (adreno_is_a623(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 16;

		gpu->ubwc_config.rgb565_predicator = 1;

		gpu->ubwc_config.uavflagprd_inv = 2;

		gpu->ubwc_config.macrotile_mode = 1;

	}
@@ -657,21 +653,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
		/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */

		gpu->ubwc_config.highest_bank_bit = 16;

		gpu->ubwc_config.rgb565_predicator = 1;

		gpu->ubwc_config.uavflagprd_inv = 2;

		gpu->ubwc_config.macrotile_mode = 1;

	}



	if (adreno_is_a663(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 13;

		gpu->ubwc_config.rgb565_predicator = 1;

		gpu->ubwc_config.uavflagprd_inv = 2;

		gpu->ubwc_config.macrotile_mode = 1;

		gpu->ubwc_config.ubwc_swizzle = 0x4;

	}



	if (adreno_is_7c3(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 14;

		gpu->ubwc_config.uavflagprd_inv = 2;

		gpu->ubwc_config.macrotile_mode = 1;

	}
@@ -695,11 +688,15 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
	BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);

	u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;

	bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;

	u8 uavflagprd_inv = 0;

	u32 hbb_hi = hbb >> 2;

	u32 hbb_lo = hbb & 3;

	u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;

	u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);



	if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))

		uavflagprd_inv = 2;



	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,

		  level2_swizzling_dis << 12 |

		  adreno_gpu->ubwc_config.rgb565_predicator << 11 |
@@ -714,7 +711,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 


	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,

		  level2_swizzling_dis << 12 | hbb_hi << 10 |

		  adreno_gpu->ubwc_config.uavflagprd_inv << 4 |

		  uavflagprd_inv << 4 |

		  adreno_gpu->ubwc_config.min_acc_len << 3 |

		  hbb_lo << 1 | ubwc_mode);