Commit 32fafaf2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-fixes-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy fixes from Vinod Koul:

 - Qualcomm QMP X1E80100 PCIe Gen4 PHY initialisation fix

 - Freescale imx8mq tuning parameter name fix

 - Samsung exynos5 fir for error code in probe()

 - Xilinx Zynqmp SGMII linkup failure fix

* tag 'phy-fixes-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resume
  phy: exynos5-usbdrd: fix error code in probe()
  phy: fsl-imx8mq-usb: fix tuning parameter name
  phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisation
parents 8d80c990 5af9b304

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

+1 −1
Original line number Diff line number Diff line
@@ -176,7 +176,7 @@ static void imx8m_get_phy_tuning_data(struct imx8mq_usb_phy *imx_phy) 
		imx_phy->comp_dis_tune =

			phy_comp_dis_tune_from_property(imx_phy->comp_dis_tune);



	if (device_property_read_u32(dev, "fsl,pcs-tx-deemph-3p5db-attenuation-db",

	if (device_property_read_u32(dev, "fsl,phy-pcs-tx-deemph-3p5db-attenuation-db",

				     &imx_phy->pcs_tx_deemph_3p5db))

		imx_phy->pcs_tx_deemph_3p5db = PHY_TUNE_DEFAULT;

	else

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+16 −7
Original line number Diff line number Diff line
@@ -1245,8 +1245,8 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
@@ -1263,6 +1263,7 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),

};



static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
@@ -1286,12 +1287,15 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b),

	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),

	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),

	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),

	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
@@ -1307,6 +1311,7 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),

};



static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
@@ -1314,6 +1319,8 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),

	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),

	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),

};



static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
@@ -1324,11 +1331,13 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),

};



static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {

drivers/phy/samsung/phy-exynos5-usbdrd.c

+1 −1
Original line number Diff line number Diff line
@@ -1745,7 +1745,7 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) 
					   sizeof(*phy_drd->regulators),

					   GFP_KERNEL);

	if (!phy_drd->regulators)

		return ENOMEM;

		return -ENOMEM;

	regulator_bulk_set_supply_names(phy_drd->regulators,

					drv_data->regulator_names,

					drv_data->n_regulators);

drivers/phy/xilinx/phy-zynqmp.c

+56 −0
Original line number Diff line number Diff line
@@ -160,6 +160,24 @@ static const char *const xpsgtr_icm_str[] = { 
/* Timeout values */

#define TIMEOUT_US			1000



/* Lane 0/1/2/3 offset */

#define DIG_8(n)		((0x4000 * (n)) + 0x1074)

#define ILL13(n)		((0x4000 * (n)) + 0x1994)

#define DIG_10(n)		((0x4000 * (n)) + 0x107c)

#define RST_DLY(n)		((0x4000 * (n)) + 0x19a4)

#define BYP_15(n)		((0x4000 * (n)) + 0x1038)

#define BYP_12(n)		((0x4000 * (n)) + 0x102c)

#define MISC3(n)		((0x4000 * (n)) + 0x19ac)

#define EQ11(n)			((0x4000 * (n)) + 0x1978)



static u32 save_reg_address[] = {

	/* Lane 0/1/2/3 Register */

	DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0),

	DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1),

	DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2),

	DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3),

};



struct xpsgtr_dev;



/**
@@ -209,6 +227,7 @@ struct xpsgtr_phy { 
 * @tx_term_fix: fix for GT issue

 * @saved_icm_cfg0: stored value of ICM CFG0 register

 * @saved_icm_cfg1: stored value of ICM CFG1 register

 * @saved_regs: registers to be saved/restored during suspend/resume

 */

struct xpsgtr_dev {

	struct device *dev;
@@ -221,6 +240,7 @@ struct xpsgtr_dev { 
	bool tx_term_fix;

	unsigned int saved_icm_cfg0;

	unsigned int saved_icm_cfg1;

	u32 *saved_regs;

};



/*
@@ -294,6 +314,32 @@ static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy, 
	writel((readl(addr) & ~clr) | set, addr);

}



/**

 * xpsgtr_save_lane_regs - Saves registers on suspend

 * @gtr_dev: pointer to phy controller context structure

 */

static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)

		gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev,

						     save_reg_address[i]);

}



/**

 * xpsgtr_restore_lane_regs - Restores registers on resume

 * @gtr_dev: pointer to phy controller context structure

 */

static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)

		xpsgtr_write(gtr_dev, save_reg_address[i],

			     gtr_dev->saved_regs[i]);

}



/*

 * Hardware Configuration

 */
@@ -837,6 +883,8 @@ static int xpsgtr_runtime_suspend(struct device *dev) 
	gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);

	gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);



	xpsgtr_save_lane_regs(gtr_dev);



	return 0;

}
@@ -847,6 +895,8 @@ static int xpsgtr_runtime_resume(struct device *dev) 
	unsigned int i;

	bool skip_phy_init;



	xpsgtr_restore_lane_regs(gtr_dev);



	icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);

	icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
@@ -994,6 +1044,12 @@ static int xpsgtr_probe(struct platform_device *pdev) 
		return ret;

	}



	gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev,

					   sizeof(save_reg_address),

					   GFP_KERNEL);

	if (!gtr_dev->saved_regs)

		return -ENOMEM;



	return 0;

}