Commit 33239152 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Stephen Boyd
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clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883 

Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
set some peripherals that has this clock as their parent. When this driver
was mainlined we could not find any active users of this SoC so we cannot
perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
device which uses this SoC appear and reported some issues in openWRT:
- https://github.com/openwrt/openwrt/issues/16054


The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
has a not defined 'periph' clock as parent. Hence, introduce it to have a
properly working clock plan for this SoC.

Fixes: 6f3b1558 ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20240910044024.120009-2-sergio.paracuellos@gmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9bf7cfdb

drivers/clk/ralink/clk-mtmips.c

+7 −2
Original line number Diff line number Diff line
@@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fixed_clocks[] = { 
	CLK_FIXED("xtal", NULL, 40000000)

};



static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {

	CLK_FIXED("xtal", NULL, 40000000),

	CLK_FIXED("periph", "xtal", 40000000)

};



static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {

	CLK_FIXED("periph", "xtal", 40000000)

};
@@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt3352_clk_data = { 
static const struct mtmips_clk_data rt3883_clk_data = {

	.clk_base = rt3883_clks_base,

	.num_clk_base = ARRAY_SIZE(rt3883_clks_base),

	.clk_fixed = rt305x_fixed_clocks,

	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),

	.clk_fixed = rt3883_fixed_clocks,

	.num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),

	.clk_factor = NULL,

	.num_clk_factor = 0,

	.clk_periph = rt5350_pherip_clks,