Commit 3389c2be authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/xe/vram: Move forcewake down to get_flat_ccs_offset() 



With SG_TILE_ADDR_RANGE use, the only thing requiring GT forcewake while
probing for vram size is the get_flat_ccs_offset(). Move the forcewake
down where it's needed.

Suggested-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251107-tile-addr-v1-2-a3014aadc2e7@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 84a6fc4c

drivers/gpu/drm/xe/xe_vram.c

+14 −10
Original line number Diff line number Diff line
@@ -183,12 +183,17 @@ static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region * 
	return 0;

}



static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)

static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)

{

	struct xe_device *xe = gt_to_xe(gt);

	unsigned int fw_ref;

	u64 offset;

	u32 reg;



	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);

	if (!fw_ref)

		return -ETIMEDOUT;



	if (GRAPHICS_VER(xe) >= 20) {

		u64 ccs_size = tile_size / 512;

		u64 offset_hi, offset_lo;
@@ -218,7 +223,10 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) 
		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;

	}



	return offset;

	xe_force_wake_put(gt_to_fw(gt), fw_ref);

	*poffset = offset;



	return 0;

}



/*
@@ -245,7 +253,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 
{

	struct xe_device *xe = tile_to_xe(tile);

	struct xe_gt *gt = tile->primary_gt;

	unsigned int fw_ref;

	u64 offset;

	u32 reg;
@@ -265,10 +272,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 
		return 0;

	}



	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);

	if (!fw_ref)

		return -ETIMEDOUT;



	/* actual size */

	if (unlikely(xe->info.platform == XE_DG1)) {

		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
@@ -281,7 +284,10 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 


	/* minus device usage */

	if (xe->info.has_flat_ccs) {

		offset = get_flat_ccs_offset(gt, *tile_size);

		int ret = get_flat_ccs_offset(gt, *tile_size, &offset);



		if (ret)

			return ret;

	} else {

		offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);

	}
@@ -289,8 +295,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 
	/* remove the tile offset so we have just the available size */

	*vram_size = offset - *tile_offset;



	xe_force_wake_put(gt_to_fw(gt), fw_ref);



	return 0;

}