Commit 33a9caa4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "New Support:

   - Qualcomm SM8650 UFS, PCIe and USB/DP Combo PHY, eUSB2 PHY, SDX75
     USB3, X1E80100 USB3 support

   - Mediatek MT8195 support

   - Rockchip RK3128 usb2 support

   - TI SGMII mode for J784S4

  Updates:

   - Qualcomm v7 register offsets updates

   - Mediatek tphy support for force phy mode switch"

* tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (34 commits)
  phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4
  phy: ti: gmii-sel: Enable SGMII mode for J784S4
  phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support
  dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding
  phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys
  dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible
  dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible
  phy: mediatek: tphy: add support force phy mode switch
  dt-bindings: phy: mediatek: tphy: add a property for force-mode switch
  phy: phy-can-transceiver: insert space after include
  phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
  dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header
  phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY
  phy: qcom-qmp: qserdes-txrx: Add v7 register offsets
  phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets
  phy: qcom-qmp: qserdes-com: Add v7 register offsets
  phy: qcom-qmp: pcs-usb: Add v7 register offsets
  phy: qcom-qmp: pcs: Add v7 register offsets
  phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
  phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
  ...
parents 4d5d604c 2029e714

Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml

+0 −12
Original line number Diff line number Diff line
@@ -16,20 +16,8 @@ properties: 
  "#phy-cells":

    const: 0



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - "#phy-cells"



additionalProperties: false
 


examples:

  - |

    phy@0 {

          compatible = "amlogic,g12a-mipi-dphy-analog";

          reg = <0x0 0xc>;

          #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml

+0 −17
Original line number Diff line number Diff line
@@ -9,16 +9,6 @@ title: Amlogic AXG shared MIPI/PCIE analog PHY 
maintainers:

  - Remi Pommarel <repk@triplefau.lt>



description: |+

  The Everything-Else Power Domains node should be the child of a syscon

  node with the required property:



  - compatible: Should be the following:

                "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"



  Refer to the bindings described in

  Documentation/devicetree/bindings/mfd/syscon.yaml



properties:

  compatible:

    const: amlogic,axg-mipi-pcie-analog-phy
@@ -31,10 +21,3 @@ required: 
  - "#phy-cells"



additionalProperties: false
 


examples:

  - |

    mpphy: phy {

          compatible = "amlogic,axg-mipi-pcie-analog-phy";

          #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ properties: 
      - items:

          - enum:

              - mediatek,mt8188-mipi-tx

              - mediatek,mt8195-mipi-tx

              - mediatek,mt8365-mipi-tx

          - const: mediatek,mt8183-mipi-tx

      - const: mediatek,mt2701-mipi-tx

Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

+9 −0
Original line number Diff line number Diff line
@@ -235,6 +235,15 @@ patternProperties: 
          Specify the flag to enable BC1.2 if support it

        type: boolean



      mediatek,force-mode:

        description:

          The force mode is used to manually switch the shared phy mode between

          USB3 and PCIe, when USB3 phy type is selected by the consumer, and

          force-mode is set, will cause phy's power and pipe toggled and force

          phy as USB3 mode which switched from default PCIe mode. But perfer to

          use the property "mediatek,syscon-type" for newer SoCs that support it.

        type: boolean



      mediatek,syscon-type:

        $ref: /schemas/types.yaml#/definitions/phandle-array

        maxItems: 1

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

+5 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ properties: 
      - qcom,sm8450-qmp-gen4x2-pcie-phy

      - qcom,sm8550-qmp-gen3x2-pcie-phy

      - qcom,sm8550-qmp-gen4x2-pcie-phy

      - qcom,sm8650-qmp-gen3x2-pcie-phy

      - qcom,sm8650-qmp-gen4x2-pcie-phy



  reg:

    minItems: 1
@@ -147,6 +149,8 @@ allOf: 
              - qcom,sm8450-qmp-gen3x2-pcie-phy

              - qcom,sm8550-qmp-gen3x2-pcie-phy

              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen3x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

    then:

      properties:

        clocks:
@@ -189,6 +193,7 @@ allOf: 
          contains:

            enum:

              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

    then:

      properties:

        resets: