Commit 33aaab6d authored by Adam Ford's avatar Adam Ford Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: beacon-rzg2m-kit: Rearrange SoC unique functions 



In preparation for adding new dev kits, move anything specific to the
RZ/G2M from the SOM-level and baseboard-levels and move them to the
kit-level.  This allows the SOM and baseboard to be reused with
other SoC's.

Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201224170502.2254683-6-aford173@gmail.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e718d563

arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi

+0 −15
Original line number Diff line number Diff line
@@ -264,21 +264,6 @@ &can1 { 
	status = "okay";

};



&du {

	pinctrl-0 = <&du_pins>;

	pinctrl-names = "default";

	status = "okay";



	clocks = <&cpg CPG_MOD 724>,

		<&cpg CPG_MOD 723>,

		<&cpg CPG_MOD 722>,

		<&versaclock5 1>,

		<&x302_clk>,

		<&versaclock5 2>;

	clock-names = "du.0", "du.1", "du.2",

		"dclkin.0", "dclkin.1", "dclkin.2";

};



&du_out_rgb {

	remote-endpoint = <&rgb_panel>;

};

arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi

+0 −5
Original line number Diff line number Diff line
@@ -13,11 +13,6 @@ memory@48000000 { 
		reg = <0x0 0x48000000 0x0 0x78000000>;

	};



	memory@600000000 {

		device_type = "memory";

		reg = <0x6 0x00000000 0x0 0x80000000>;

	};



	osc_32k: osc_32k {

		compatible = "fixed-clock";

		#clock-cells = <0>;

arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts

+20 −0
Original line number Diff line number Diff line
@@ -26,6 +26,26 @@ aliases { 
	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory@600000000 {

		device_type = "memory";

		reg = <0x6 0x00000000 0x0 0x80000000>;

	};

};



&du {

	pinctrl-0 = <&du_pins>;

	pinctrl-names = "default";

	status = "okay";



	clocks = <&cpg CPG_MOD 724>,

		 <&cpg CPG_MOD 723>,

		 <&cpg CPG_MOD 722>,

		 <&versaclock5 1>,

		 <&x302_clk>,

		 <&versaclock5 2>;

	clock-names = "du.0", "du.1", "du.2",

		      "dclkin.0", "dclkin.1", "dclkin.2";

};



/* Reference versaclock instead of audio_clk_a */