Commit 33bedb92 authored by Dave Jiang's avatar Dave Jiang
Browse files

Merge branch 'for-6.19/cxl-prm' into cxl-for-next 

- Simplify cxl_rd_ops allocation
- Group xor arithmetric setup code
- Remove local variable @inc in cxl_port_setup_targets()
parents 482dc84e 7e71fa6e

drivers/cxl/acpi.c

+4 −11
Original line number Diff line number Diff line
@@ -469,8 +469,6 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, 
		ig = CXL_DECODER_MIN_GRANULARITY;

	cxld->interleave_granularity = ig;



	cxl_setup_extended_linear_cache(cxlrd);



	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {

		if (ways != 1 && ways != 3) {

			cxims_ctx = (struct cxl_cxims_context) {
@@ -486,18 +484,13 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, 
				return -EINVAL;

			}

		}

		cxlrd->ops.hpa_to_spa = cxl_apply_xor_maps;

		cxlrd->ops.spa_to_hpa = cxl_apply_xor_maps;

	}



	cxlrd->qos_class = cfmws->qtg_id;



	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {

		cxlrd->ops = kzalloc(sizeof(*cxlrd->ops), GFP_KERNEL);

		if (!cxlrd->ops)

			return -ENOMEM;

	cxl_setup_extended_linear_cache(cxlrd);



		cxlrd->ops->hpa_to_spa = cxl_apply_xor_maps;

		cxlrd->ops->spa_to_hpa = cxl_apply_xor_maps;

	}

	cxlrd->qos_class = cfmws->qtg_id;



	rc = cxl_decoder_add(cxld);

	if (rc)

drivers/cxl/core/port.c

+0 −1
Original line number Diff line number Diff line
@@ -459,7 +459,6 @@ static void cxl_root_decoder_release(struct device *dev) 
	if (atomic_read(&cxlrd->region_id) >= 0)

		memregion_free(atomic_read(&cxlrd->region_id));

	__cxl_decoder_release(&cxlrd->cxlsd.cxld);

	kfree(cxlrd->ops);

	kfree(cxlrd);

}

drivers/cxl/core/region.c

+7 −18
Original line number Diff line number Diff line
@@ -1371,7 +1371,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, 
				  struct cxl_endpoint_decoder *cxled)

{

	struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);

	int parent_iw, parent_ig, ig, iw, rc, inc = 0, pos = cxled->pos;

	int parent_iw, parent_ig, ig, iw, rc, pos = cxled->pos;

	struct cxl_port *parent_port = to_cxl_port(port->dev.parent);

	struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);

	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
@@ -1563,9 +1563,8 @@ static int cxl_port_setup_targets(struct cxl_port *port, 
		cxlsd->target[cxl_rr->nr_targets_set] = ep->dport;

		cxlsd->cxld.target_map[cxl_rr->nr_targets_set] = ep->dport->port_id;

	}

	inc = 1;

	cxl_rr->nr_targets_set++;

out_target_set:

	cxl_rr->nr_targets_set += inc;

	dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n",

		dev_name(port->uport_dev), dev_name(&port->dev),

		cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport_dev),
@@ -2968,16 +2967,6 @@ static bool cxl_is_hpa_in_chunk(u64 hpa, struct cxl_region *cxlr, int pos) 
	return false;

}



static bool has_hpa_to_spa(struct cxl_root_decoder *cxlrd)

{

	return cxlrd->ops && cxlrd->ops->hpa_to_spa;

}



static bool has_spa_to_hpa(struct cxl_root_decoder *cxlrd)

{

	return cxlrd->ops && cxlrd->ops->spa_to_hpa;

}



#define CXL_POS_ZERO 0

/**

 * cxl_validate_translation_params
@@ -3151,8 +3140,8 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, 
	hpa = hpa_offset + p->res->start + p->cache_size;



	/* Root decoder translation overrides typical modulo decode */

	if (has_hpa_to_spa(cxlrd))

		hpa = cxlrd->ops->hpa_to_spa(cxlrd, hpa);

	if (cxlrd->ops.hpa_to_spa)

		hpa = cxlrd->ops.hpa_to_spa(cxlrd, hpa);



	if (!cxl_resource_contains_addr(p->res, hpa)) {

		dev_dbg(&cxlr->dev,
@@ -3161,7 +3150,7 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, 
	}



	/* Simple chunk check, by pos & gran, only applies to modulo decodes */

	if (!has_hpa_to_spa(cxlrd) && (!cxl_is_hpa_in_chunk(hpa, cxlr, pos)))

	if (!cxlrd->ops.hpa_to_spa && !cxl_is_hpa_in_chunk(hpa, cxlr, pos))

		return ULLONG_MAX;



	return hpa;
@@ -3194,8 +3183,8 @@ static int region_offset_to_dpa_result(struct cxl_region *cxlr, u64 offset, 
	 * If the root decoder has SPA to CXL HPA callback, use it. Otherwise

	 * CXL HPA is assumed to equal SPA.

	 */

	if (has_spa_to_hpa(cxlrd)) {

		hpa = cxlrd->ops->spa_to_hpa(cxlrd, p->res->start + offset);

	if (cxlrd->ops.spa_to_hpa) {

		hpa = cxlrd->ops.spa_to_hpa(cxlrd, p->res->start + offset);

		hpa_offset = hpa - p->res->start;

	} else {

		hpa_offset = offset;

drivers/cxl/cxl.h

+1 −1
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ struct cxl_root_decoder { 
	void *platform_data;

	struct mutex range_lock;

	int qos_class;

	struct cxl_rd_ops *ops;

	struct cxl_rd_ops ops;

	struct cxl_switch_decoder cxlsd;

};