Commit 3409f843 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Neil Armstrong
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ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock 



Device-tree expects absent clocks to be specified as <0> (instead of
using <>). This fixes using the FCLK4/FCLK3 clocks as they are now
seen at their correct index (while before they were recognized, but at
the correct index - resulting in the hardware using a different clock
than what the kernel sees).

Fixes: 802cff46 ("ARM: dts: amlogic: meson8: switch to the new PWM controller binding")
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250420164801.330505-2-martin.blumenstingl@googlemail.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent 0af2f6be

arch/arm/boot/dts/amlogic/meson8.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ analog_top: analog-top@81a8 { 
	pwm_ef: pwm@86c0 {

		compatible = "amlogic,meson8-pwm-v2";

		clocks = <&xtal>,

			 <>, /* unknown/untested, the datasheet calls it "Video PLL" */

			 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */

			 <&clkc CLKID_FCLK_DIV4>,

			 <&clkc CLKID_FCLK_DIV3>;

		reg = <0x86c0 0x10>;
@@ -705,7 +705,7 @@ timer@600 { 
&pwm_ab {

	compatible = "amlogic,meson8-pwm-v2";

	clocks = <&xtal>,

		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */

		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_FCLK_DIV3>;

};
@@ -713,7 +713,7 @@ &pwm_ab { 
&pwm_cd {

	compatible = "amlogic,meson8-pwm-v2";

	clocks = <&xtal>,

		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */

		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_FCLK_DIV3>;

};