Unverified Commit 341d72eb authored by Marek Vasut's avatar Marek Vasut Committed by Stephen Boyd
Browse files

dt-bindings: clk: rs9: Fix DIF pattern match 



The pattern match [0-19] is incorrect and does not cover range of 0..19,
use pattern 1?[0-9] to cover range 0..19 instead. Update the example to
validate all parts of the pattern match and prevent such failures in the
future.

Fixes: 26c1bc67 ("dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator")
Signed-off-by: default avatarMarek Vasut <marek.vasut@mailbox.org>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 37eb3349

Documentation/devicetree/bindings/clock/renesas,9series.yaml

+10 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ properties: 
    description: Output clock down spread in pcm (1/1000 of percent)



patternProperties:

  "^DIF[0-19]$":

  "^DIF1?[0-9]$":

    type: object

    description:

      Description of one of the outputs (DIF0..DIF19).
@@ -107,6 +107,15 @@ examples: 
            DIF0 {

                renesas,slew-rate = <3000000>;

            };



            /* Not present on 9FGV0241, used for DT validation only */

            DIF2 {

                renesas,slew-rate = <2000000>;

            };



            DIF19 {

                renesas,slew-rate = <3000000>;

            };

        };

    };