Unverified Commit 343855d2 authored by Frank Wunderlich's avatar Frank Wunderlich Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt7988: Add CPU OPP table for clock scaling

parent b87cf198
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+38 −0
Original line number Diff line number Diff line
@@ -21,6 +21,10 @@ cpu@0 {
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu@1 {
@@ -28,6 +32,10 @@ cpu@1 {
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu@2 {
@@ -35,6 +43,10 @@ cpu@2 {
			reg = <0x2>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu@3 {
@@ -42,6 +54,32 @@ cpu@3 {
			reg = <0x3>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
		};

		cluster0_opp: opp-table-0 {
			compatible = "operating-points-v2";
			opp-shared;

			opp-800000000 {
				opp-hz = /bits/ 64 <800000000>;
				opp-microvolt = <850000>;
			};
			opp-1100000000 {
				opp-hz = /bits/ 64 <1100000000>;
				opp-microvolt = <850000>;
			};
			opp-1500000000 {
				opp-hz = /bits/ 64 <1500000000>;
				opp-microvolt = <850000>;
			};
			opp-1800000000 {
				opp-hz = /bits/ 64 <1800000000>;
				opp-microvolt = <900000>;
			};
		};
	};