Commit 34be7519 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/mm' into x86/core, to resolve conflicts 



 Conflicts:
	arch/x86/mm/numa.c
	arch/x86/mm/pgtable.c

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 69cb33e2 1b3f2bd0

arch/x86/Kconfig.assembler

+0 −4
Original line number Diff line number Diff line
@@ -15,10 +15,6 @@ config AS_SHA256_NI 
	def_bool $(as-instr,sha256msg1 %xmm0$(comma)%xmm1)

	help

	  Supported by binutils >= 2.24 and LLVM integrated assembler

config AS_TPAUSE

	def_bool $(as-instr,tpause %ecx)

	help

	  Supported by binutils >= 2.31.1 and LLVM integrated assembler >= V7



config AS_GFNI

	def_bool $(as-instr,vgf2p8mulb %xmm0$(comma)%xmm1$(comma)%xmm2)

arch/x86/include/asm/mwait.h

+28 −38
Original line number Diff line number Diff line
@@ -25,29 +25,31 @@ 
#define TPAUSE_C01_STATE		1

#define TPAUSE_C02_STATE		0



static __always_inline void __monitor(const void *eax, unsigned long ecx,

			     unsigned long edx)

static __always_inline void __monitor(const void *eax, u32 ecx, u32 edx)

{

	/* "monitor %eax, %ecx, %edx;" */

	asm volatile(".byte 0x0f, 0x01, 0xc8;"

		     :: "a" (eax), "c" (ecx), "d"(edx));

	/*

	 * Use the instruction mnemonic with implicit operands, as the LLVM

	 * assembler fails to assemble the mnemonic with explicit operands:

	 */

	asm volatile("monitor" :: "a" (eax), "c" (ecx), "d" (edx));

}



static __always_inline void __monitorx(const void *eax, unsigned long ecx,

			      unsigned long edx)

static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx)

{

	/* "monitorx %eax, %ecx, %edx;" */

	asm volatile(".byte 0x0f, 0x01, 0xfa;"

	/* "monitorx %eax, %ecx, %edx" */

	asm volatile(".byte 0x0f, 0x01, 0xfa"

		     :: "a" (eax), "c" (ecx), "d"(edx));

}



static __always_inline void __mwait(unsigned long eax, unsigned long ecx)

static __always_inline void __mwait(u32 eax, u32 ecx)

{

	mds_idle_clear_cpu_buffers();



	/* "mwait %eax, %ecx;" */

	asm volatile(".byte 0x0f, 0x01, 0xc9;"

		     :: "a" (eax), "c" (ecx));

	/*

	 * Use the instruction mnemonic with implicit operands, as the LLVM

	 * assembler fails to assemble the mnemonic with explicit operands:

	 */

	asm volatile("mwait" :: "a" (eax), "c" (ecx));

}



/*
@@ -76,13 +78,12 @@ static __always_inline void __mwait(unsigned long eax, unsigned long ecx) 
 * EAX                     (logical) address to monitor

 * ECX                     #GP if not zero

 */

static __always_inline void __mwaitx(unsigned long eax, unsigned long ebx,

				     unsigned long ecx)

static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx)

{

	/* No MDS buffer clear as this is AMD/HYGON only */



	/* "mwaitx %eax, %ebx, %ecx;" */

	asm volatile(".byte 0x0f, 0x01, 0xfb;"

	/* "mwaitx %eax, %ebx, %ecx" */

	asm volatile(".byte 0x0f, 0x01, 0xfb"

		     :: "a" (eax), "b" (ebx), "c" (ecx));

}
@@ -95,12 +96,11 @@ static __always_inline void __mwaitx(unsigned long eax, unsigned long ebx, 
 * executing mwait, it would otherwise go unnoticed and the next tick

 * would not be reprogrammed accordingly before mwait ever wakes up.

 */

static __always_inline void __sti_mwait(unsigned long eax, unsigned long ecx)

static __always_inline void __sti_mwait(u32 eax, u32 ecx)

{

	mds_idle_clear_cpu_buffers();

	/* "mwait %eax, %ecx;" */

	asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"

		     :: "a" (eax), "c" (ecx));



	asm volatile("sti; mwait" :: "a" (eax), "c" (ecx));

}



/*
@@ -113,16 +113,13 @@ static __always_inline void __sti_mwait(unsigned long eax, unsigned long ecx) 
 * New with Core Duo processors, MWAIT can take some hints based on CPU

 * capability.

 */

static __always_inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)

static __always_inline void mwait_idle_with_hints(u32 eax, u32 ecx)

{

	if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {

		if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {

			mb();

			clflush((void *)&current_thread_info()->flags);

			mb();

		}

		const void *addr = &current_thread_info()->flags;



		__monitor((void *)&current_thread_info()->flags, 0, 0);

		alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr));

		__monitor(addr, 0, 0);



		if (!need_resched()) {

			if (ecx & 1) {
@@ -144,16 +141,9 @@ static __always_inline void mwait_idle_with_hints(unsigned long eax, unsigned lo 
 */

static inline void __tpause(u32 ecx, u32 edx, u32 eax)

{

	/* "tpause %ecx, %edx, %eax;" */

	#ifdef CONFIG_AS_TPAUSE

	asm volatile("tpause %%ecx\n"

		     :

		     : "c"(ecx), "d"(edx), "a"(eax));

	#else

	asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1\t\n"

		     :

		     : "c"(ecx), "d"(edx), "a"(eax));

	#endif

	/* "tpause %ecx" */

	asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1"

		     :: "c" (ecx), "d" (edx), "a" (eax));

}



#endif /* _ASM_X86_MWAIT_H */

arch/x86/include/asm/page_32_types.h

+0 −1
Original line number Diff line number Diff line
@@ -73,7 +73,6 @@ extern unsigned int __VMALLOC_RESERVE; 
extern int sysctl_legacy_va_layout;



extern void find_low_pfn_range(void);

extern void setup_bootmem_allocator(void);



#endif	/* !__ASSEMBLER__ */

arch/x86/include/asm/pgtable-2level_types.h

+0 −2
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ typedef union { 
} pte_t;

#endif	/* !__ASSEMBLER__ */



#define SHARED_KERNEL_PMD	0



#define ARCH_PAGE_TABLE_SYNC_MASK	PGTBL_PMD_MODIFIED



/*

arch/x86/include/asm/pgtable-3level_types.h

+1 −3
Original line number Diff line number Diff line
@@ -27,9 +27,7 @@ typedef union { 
} pmd_t;

#endif	/* !__ASSEMBLER__ */



#define SHARED_KERNEL_PMD	(!static_cpu_has(X86_FEATURE_PTI))



#define ARCH_PAGE_TABLE_SYNC_MASK	(SHARED_KERNEL_PMD ? 0 : PGTBL_PMD_MODIFIED)

#define ARCH_PAGE_TABLE_SYNC_MASK	PGTBL_PMD_MODIFIED



/*

 * PGDIR_SHIFT determines what a top-level page table entry can map