Commit 34d127e2 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/cdclk: Fix voltage_level programming edge case 



Currently we only consider the relationship of the
old and new CDCLK frequencies when determining whether
to do the repgramming from intel_set_cdclk_pre_plane_update()
or intel_set_cdclk_post_plane_update().

It is technically possible to have a situation where the
CDCLK frequency is decreasing, but the voltage_level is
increasing due a DDI port. In this case we should bump
the voltage level already in intel_set_cdclk_pre_plane_update()
(so that the voltage_level will have been increased by the
time the port gets enabled), while leaving the CDCLK frequency
unchanged (as active planes/etc. may still depend on it).
We can then reduce the CDCLK frequency to its final value
from intel_set_cdclk_post_plane_update().

In order to handle that correctly we shall construct a
suitable amalgam of the old and new cdclk states in
intel_set_cdclk_pre_plane_update().

And we can simply call intel_set_cdclk() unconditionally
in both places as it will not do anything if nothing actually
changes vs. the current hw state.

v2: Handle cdclk_state->disable_pipes
v3: Only synchronize the cd2x update against the pipe's vblank
    when the cdclk frequency is changing during the current
    commit phase (Gustavo)

Cc: stable@vger.kernel.org
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-3-ville.syrjala@linux.intel.com
parent 3aecee90

drivers/gpu/drm/i915/display/intel_cdclk.c

+27 −10
Original line number Diff line number Diff line
@@ -2600,7 +2600,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 
		intel_atomic_get_old_cdclk_state(state);

	const struct intel_cdclk_state *new_cdclk_state =

		intel_atomic_get_new_cdclk_state(state);

	enum pipe pipe = new_cdclk_state->pipe;

	struct intel_cdclk_config cdclk_config;

	enum pipe pipe;



	if (!intel_cdclk_changed(&old_cdclk_state->actual,

				 &new_cdclk_state->actual))
@@ -2609,12 +2610,25 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 
	if (IS_DG2(i915))

		intel_cdclk_pcode_pre_notify(state);



	if (new_cdclk_state->disable_pipes ||

	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {

		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);

	if (new_cdclk_state->disable_pipes) {

		cdclk_config = new_cdclk_state->actual;

		pipe = INVALID_PIPE;

	} else {

		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {

			cdclk_config = new_cdclk_state->actual;

			pipe = new_cdclk_state->pipe;

		} else {

			cdclk_config = old_cdclk_state->actual;

			pipe = INVALID_PIPE;

		}



		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);

		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,

						 old_cdclk_state->actual.voltage_level);

	}



	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);



	intel_set_cdclk(i915, &cdclk_config, pipe);

}



/**
@@ -2632,7 +2646,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 
		intel_atomic_get_old_cdclk_state(state);

	const struct intel_cdclk_state *new_cdclk_state =

		intel_atomic_get_new_cdclk_state(state);

	enum pipe pipe = new_cdclk_state->pipe;

	enum pipe pipe;



	if (!intel_cdclk_changed(&old_cdclk_state->actual,

				 &new_cdclk_state->actual))
@@ -2642,12 +2656,15 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 
		intel_cdclk_pcode_post_notify(state);



	if (!new_cdclk_state->disable_pipes &&

	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {

	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)

		pipe = new_cdclk_state->pipe;

	else

		pipe = INVALID_PIPE;



	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);



	intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);

}

}



static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)

{