Commit 34e48901 authored by Neal Frager's avatar Neal Frager Committed by Michal Simek
Browse files

arm64: zynqmp: Add output-enable pins to SOMs 



Now that the zynqmp pinctrl driver supports the tri-state registers, make
sure that the pins requiring output-enable are configured appropriately for
SOMs.

Without it, all tristate setting for MIOs, which are not related to SOM
itself, are using default configuration which is not correct setting.
It means SDs, USBs, ethernet, etc. are not working properly.

In past it was fixed through calling tristate configuration via bootcmd:
usb_init=mw 0xFF180208 2020
kv260_gem3=mw 0xFF18020C 0xFC0 && gpio toggle gpio@ff0a000038 && \
  gpio toggle gpio@ff0a000038

Signed-off-by: default avatarNeal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/9270938b48c8939ac5dca4ac2c59f1c4a8c564d8.1704728353.git.michal.simek@amd.com


Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
parent 5710ea6a

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+5 −0
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ conf-rx { 
		conf-tx {

			pins = "MIO36";

			bias-disable;

			output-enable;

		};



		mux {
@@ -236,6 +237,7 @@ conf-rx { 
		conf-bootstrap {

			pins = "MIO71", "MIO73", "MIO75";

			bias-disable;

			output-enable;

			low-power-disable;

		};
@@ -243,6 +245,7 @@ conf-tx { 
			pins = "MIO64", "MIO65", "MIO66",

				"MIO67", "MIO68", "MIO69";

			bias-disable;

			output-enable;

			low-power-enable;

		};
@@ -251,6 +254,7 @@ conf-mdio { 
			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

			bias-disable;

			output-enable;

		};



		mux-mdio {
@@ -281,6 +285,7 @@ conf-tx { 
			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",

			"MIO60", "MIO61", "MIO62", "MIO63";

			bias-disable;

			output-enable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+5 −0
Original line number Diff line number Diff line
@@ -168,6 +168,7 @@ conf-rx { 
		conf-tx {

			pins = "MIO36";

			bias-disable;

			output-enable;

		};



		mux {
@@ -219,6 +220,7 @@ conf-rx { 
		conf-bootstrap {

			pins = "MIO71", "MIO73", "MIO75";

			bias-disable;

			output-enable;

			low-power-disable;

		};
@@ -226,6 +228,7 @@ conf-tx { 
			pins = "MIO64", "MIO65", "MIO66",

				"MIO67", "MIO68", "MIO69";

			bias-disable;

			output-enable;

			low-power-enable;

		};
@@ -234,6 +237,7 @@ conf-mdio { 
			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

			bias-disable;

			output-enable;

		};



		mux-mdio {
@@ -264,6 +268,7 @@ conf-tx { 
			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",

			"MIO60", "MIO61", "MIO62", "MIO63";

			bias-disable;

			output-enable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};