Commit 34f7151d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.15-2025-05-14' of... 

Merge tag 'amd-drm-fixes-6.15-2025-05-14' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.15-2025-05-14:

amdgpu:
- Fix CSA unmap
- Fix MALL size reporting on GFX11.5
- AUX fix
- DCN 3.5 fix
- VRR fix
- DP MST fix
- DML 2.1 fixes
- Silence DP AUX spam
- DCN 4.0.1 cursor fix
- VCN 4.0.5 fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250514185117.758496-1-alexander.deucher@amd.com
parents 82f2b0b9 ee7360fc

drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, 
	struct drm_exec exec;

	int r;



	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);

	drm_exec_init(&exec, 0, 0);

	drm_exec_until_all_locked(&exec) {

		r = amdgpu_vm_lock_pd(vm, &exec, 0);

		if (likely(!r))

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+12 −0
Original line number Diff line number Diff line
@@ -752,6 +752,18 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
	adev->gmc.vram_type = vram_type;

	adev->gmc.vram_vendor = vram_vendor;



	/* The mall_size is already calculated as mall_size_per_umc * num_umc.

	 * However, for gfx1151, which features a 2-to-1 UMC mapping,

	 * the result must be multiplied by 2 to determine the actual mall size.

	 */

	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(11, 5, 1):

		adev->gmc.mall_size *= 2;

		break;

	default:

		break;

	}



	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(11, 0, 0):

	case IP_VERSION(11, 0, 1):

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

+8 −0
Original line number Diff line number Diff line
@@ -1023,6 +1023,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 
			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |

			VCN_RB1_DB_CTRL__EN_MASK);



	/* Keeping one read-back to ensure all register writes are done, otherwise

	 * it may introduce race conditions */

	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);



	return 0;

}
@@ -1205,6 +1209,10 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 
	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);

	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);



	/* Keeping one read-back to ensure all register writes are done, otherwise

	 * it may introduce race conditions */

	RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);



	return 0;

}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+4 −1
Original line number Diff line number Diff line
@@ -372,6 +372,8 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev, 
static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,

					      struct dm_crtc_state *new_state)

{

	if (new_state->stream->adjust.timing_adjust_pending)

		return true;

	if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)

		return true;

	else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
@@ -12763,7 +12765,8 @@ int amdgpu_dm_process_dmub_aux_transfer_sync( 
		/* The reply is stored in the top nibble of the command. */

		payload->reply[0] = (adev->dm.dmub_notify->aux_reply.command >> 4) & 0xF;



	if (!payload->write && p_notify->aux_reply.length)

	/*write req may receive a byte indicating partially written number as well*/

	if (p_notify->aux_reply.length)

		memcpy(payload->data, p_notify->aux_reply.data,

				p_notify->aux_reply.length);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+11 −5
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
	enum aux_return_code_type operation_result;

	struct amdgpu_device *adev;

	struct ddc_service *ddc;

	uint8_t copy[16];



	if (WARN_ON(msg->size > 16))

		return -E2BIG;
@@ -77,6 +78,11 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
			(msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;

	payload.defer_delay = 0;



	if (payload.write) {

		memcpy(copy, msg->buffer, msg->size);

		payload.data = copy;

	}



	result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,

				      &operation_result);
@@ -100,9 +106,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
	 */

	if (payload.write && result >= 0) {

		if (result) {

			/*one byte indicating partially written bytes. Force 0 to retry*/

			drm_info(adev_to_drm(adev), "amdgpu: AUX partially written\n");

			result = 0;

			/*one byte indicating partially written bytes*/

			drm_dbg_dp(adev_to_drm(adev), "amdgpu: AUX partially written\n");

			result = payload.data[0];

		} else if (!payload.reply[0])

			/*I2C_ACK|AUX_ACK*/

			result = msg->size;
@@ -127,11 +133,11 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
			break;

		}



		drm_info(adev_to_drm(adev), "amdgpu: DP AUX transfer fail:%d\n", operation_result);

		drm_dbg_dp(adev_to_drm(adev), "amdgpu: DP AUX transfer fail:%d\n", operation_result);

	}



	if (payload.reply[0])

		drm_info(adev_to_drm(adev), "amdgpu: AUX reply command not ACK: 0x%02x.",

		drm_dbg_dp(adev_to_drm(adev), "amdgpu: AUX reply command not ACK: 0x%02x.",

			payload.reply[0]);



	return result;