Commit 354fc6c5 authored by Abel Vesa's avatar Abel Vesa Committed by Vinod Koul
Browse files

phy: qcom-qmp: pcs-pcie: Add v6 register offsets 



The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated
header file.

Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 5f705402

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

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@@ -29,6 +29,7 @@ 
#include "phy-qcom-qmp-pcs-pcie-v4_20.h"

#include "phy-qcom-qmp-pcs-pcie-v5.h"

#include "phy-qcom-qmp-pcs-pcie-v5_20.h"

#include "phy-qcom-qmp-pcs-pcie-v6.h"

#include "phy-qcom-qmp-pcie-qhp.h"



/* QPHY_SW_RESET bit */

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h

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+15 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_

#define QCOM_PHY_QMP_PCS_PCIE_V6_H_



/* Only for QMP V6 PHY - PCIE have different offsets than V5 */

#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2	0x0c

#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4	0x14

#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x20

#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS		0x94



#endif