Commit 35636068 authored by Hans Zhang's avatar Hans Zhang Committed by Manivannan Sadhasivam
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dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6 



Update the PCI Endpoint (EP) device tree binding documentation to
include PCIe Gen5 and Gen6 support for the `max-link-speed` property.
Similar to the Host Controller binding, the original EP binding
limited this value to 1~4 (Gen1~Gen4). With current SoCs requiring
Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns
the EP binding with the kernel's PCIe 6.0 capabilities.

Signed-off-by: default avatarHans Zhang <18255117159@163.com>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250529021026.475861-3-18255117159@163.com
parent be84da3e

Documentation/devicetree/bindings/pci/pci-ep.yaml

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ properties: 


  max-link-speed:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 1, 2, 3, 4 ]

    enum: [ 1, 2, 3, 4, 5, 6 ]



  msi-map:

    description: |