Commit 35667a03 authored by Dnyaneshwar Bhadane's avatar Dnyaneshwar Bhadane Committed by Matt Roper
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drm/xe/pciid: Add new PCI id for ARL 



Add new PCI id for ARL platform.

v2: Fix typo in PCI id (SaiTeja)

Signed-off-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: default avatarSai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240912115906.2730577-1-dnyaneshwar.bhadane@intel.com
parent dc0dce6d

include/drm/intel/xe_pciids.h

+2 −1
Original line number Diff line number Diff line
@@ -181,7 +181,8 @@ 
	MACRO__(0x7D41, ## __VA_ARGS__),	\

	MACRO__(0x7D51, ## __VA_ARGS__),        \

	MACRO__(0x7D67, ## __VA_ARGS__),	\

	MACRO__(0x7DD1, ## __VA_ARGS__)

	MACRO__(0x7DD1, ## __VA_ARGS__),	\

	MACRO__(0xB640, ## __VA_ARGS__)



/* MTL */

#define XE_MTL_IDS(MACRO__, ...)		\