Commit 358b3774 authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
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drm/amdgpu: Enable devcoredump for JPEG5_0_1 



Add register list and enable devcoredump for JPEG5_0_1

V2: (Lijo)
- remove version specific callbacks and use simplified helper functions

V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 08527cb5

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

+47 −2
Original line number Diff line number Diff line
@@ -52,6 +52,47 @@ static int amdgpu_ih_srcid_jpeg[] = { 
	VCN_5_0__SRCID__JPEG9_DECODE,

};



static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = {

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS),

};



static int jpeg_v5_0_1_core_reg_offset(u32 pipe)

{

	if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3)
@@ -145,6 +186,10 @@ static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 
		}

	}



	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1));

	if (r)

		return r;



	return 0;

}
@@ -635,8 +680,8 @@ static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { 
	.post_soft_reset = NULL,

	.set_clockgating_state = jpeg_v5_0_1_set_clockgating_state,

	.set_powergating_state = jpeg_v5_0_1_set_powergating_state,

	.dump_ip_state = NULL,

	.print_ip_state = NULL,

	.dump_ip_state = amdgpu_jpeg_dump_ip_state,

	.print_ip_state = amdgpu_jpeg_print_ip_state,

};



static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = {

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h

+61 −0
Original line number Diff line number Diff line
@@ -26,4 +26,65 @@ 


extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block;



#define regUVD_JRBC0_UVD_JRBC_RB_WPTR             0x0640

#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX    1

#define regUVD_JRBC0_UVD_JRBC_STATUS              0x0649

#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX     1

#define regUVD_JRBC0_UVD_JRBC_RB_RPTR             0x064a

#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX    1

#define regUVD_JRBC1_UVD_JRBC_RB_WPTR             0x0000

#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC1_UVD_JRBC_STATUS              0x0009

#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC1_UVD_JRBC_RB_RPTR             0x000a

#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC2_UVD_JRBC_RB_WPTR             0x0040

#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC2_UVD_JRBC_STATUS              0x0049

#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC2_UVD_JRBC_RB_RPTR             0x004a

#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC3_UVD_JRBC_RB_WPTR             0x0080

#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC3_UVD_JRBC_STATUS              0x0089

#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC3_UVD_JRBC_RB_RPTR             0x008a

#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC4_UVD_JRBC_RB_WPTR             0x00c0

#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC4_UVD_JRBC_STATUS              0x00c9

#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC4_UVD_JRBC_RB_RPTR             0x00ca

#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC5_UVD_JRBC_RB_WPTR             0x0100

#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC5_UVD_JRBC_STATUS              0x0109

#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC5_UVD_JRBC_RB_RPTR             0x010a

#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC6_UVD_JRBC_RB_WPTR             0x0140

#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC6_UVD_JRBC_STATUS              0x0149

#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC6_UVD_JRBC_RB_RPTR             0x014a

#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC7_UVD_JRBC_RB_WPTR             0x0180

#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC7_UVD_JRBC_STATUS              0x0189

#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC7_UVD_JRBC_RB_RPTR             0x018a

#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC8_UVD_JRBC_RB_WPTR             0x01c0

#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX    0

#define regUVD_JRBC8_UVD_JRBC_STATUS              0x01c9

#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX     0

#define regUVD_JRBC8_UVD_JRBC_RB_RPTR             0x01ca

#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX    0

#define regUVD_JRBC9_UVD_JRBC_RB_WPTR             0x0440

#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX    1

#define regUVD_JRBC9_UVD_JRBC_STATUS              0x0449

#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX     1

#define regUVD_JRBC9_UVD_JRBC_RB_RPTR             0x044a

#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX    1



#endif /* __JPEG_V5_0_0_H__ */