Commit 35c1d966 authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
Browse files

drm/amd/display: Fix handling duplicate planes on one stream 



[why]
DML2 does not handle the case when we have
a single stream sourcing 2 or more planes
that are duplicates of one another. To properly
handle this scenario, pipe index to plane index
mapping is used to decide which plane is being
processed and programmed.

[how]
Create static array of pipe index to plane index map.
Populate the array properly and use in appropriate places.

Reviewed-by: default avatarXi (Alex) Liu <xi.liu@amd.com>
Acked-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarSung Joon Kim <sungkim@amd.com>
Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ed6e2782

drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

+28 −17
Original line number Diff line number Diff line
@@ -55,10 +55,11 @@ struct dc_pipe_mapping_scratch { 
	struct dc_plane_pipe_pool pipe_pool;

};



static bool get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane,

	unsigned int stream_id, unsigned int *plane_id)

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,

	unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)

{

	int i, j;

	bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;



	if (!plane_id)

		return false;
@@ -66,7 +67,8 @@ static bool get_plane_id(const struct dc_state *state, const struct dc_plane_sta 
	for (i = 0; i < state->stream_count; i++) {

		if (state->streams[i]->stream_id == stream_id) {

			for (j = 0; j < state->stream_status[i].plane_count; j++) {

				if (state->stream_status[i].plane_states[j] == plane) {

				if (state->stream_status[i].plane_states[j] == plane &&

					(!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) {

					*plane_id = (i << 16) | j;

					return true;

				}
@@ -123,8 +125,9 @@ static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx, 
	unsigned int plane_id_assigned_to_pipe;



	for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

		if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(state, state->res_ctx.pipe_ctx[i].plane_state,

			state->res_ctx.pipe_ctx[i].stream->stream_id, &plane_id_assigned_to_pipe)) {

		if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

			state->res_ctx.pipe_ctx[i].stream->stream_id,

			ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

			if (plane_id_assigned_to_pipe == plane_id)

				return &state->res_ctx.pipe_ctx[i];

		}
@@ -141,8 +144,9 @@ static unsigned int find_pipes_assigned_to_plane(struct dml2_context *ctx, 
	unsigned int plane_id_assigned_to_pipe;



	for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

		if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(state, state->res_ctx.pipe_ctx[i].plane_state,

			state->res_ctx.pipe_ctx[i].stream->stream_id, &plane_id_assigned_to_pipe)) {

		if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

			state->res_ctx.pipe_ctx[i].stream->stream_id,

			ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

			if (plane_id_assigned_to_pipe == plane_id)

				pipes[num_found++] = i;

		}
@@ -609,6 +613,7 @@ static struct pipe_ctx *assign_pipes_to_plane(struct dml2_context *ctx, struct d 
		const struct dc_plane_state *plane,

		int odm_factor,

		int mpc_factor,

		int plane_index,

		struct dc_plane_pipe_pool *pipe_pool,

		const struct dc_state *existing_state)

{
@@ -620,7 +625,7 @@ static struct pipe_ctx *assign_pipes_to_plane(struct dml2_context *ctx, struct d 
	unsigned int next_pipe_to_assign;

	int odm_slice, mpc_slice;



	if (!get_plane_id(state, plane, stream->stream_id, &plane_id)) {

	if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) {

		ASSERT(false);

		return master_pipe;

	}
@@ -667,12 +672,16 @@ static void free_pipe(struct pipe_ctx *pipe) 
}



static void free_unused_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state,

	const struct dc_plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id)

	const struct dc_plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id, int plane_index)

{

	int i;

	bool is_plane_duplicate = ctx->v20.scratch.plane_duplicate_exists;



	for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

		if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

			state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id &&

			(!is_plane_duplicate || (is_plane_duplicate &&

			ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index)) &&

			!is_pipe_used(pool, state->res_ctx.pipe_ctx[i].pipe_idx)) {

			free_pipe(&state->res_ctx.pipe_ctx[i]);

		}
@@ -717,19 +726,20 @@ static void map_pipes_for_stream(struct dml2_context *ctx, struct dc_state *stat 
}



static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state, const struct dc_stream_state *stream, const struct dc_plane_state *plane,

		struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)

		int plane_index, struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)

{

	int odm_slice_index;

	unsigned int plane_id;

	struct pipe_ctx *master_pipe = NULL;

	int i;



	if (!get_plane_id(state, plane, stream->stream_id, &plane_id)) {

	if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) {

		ASSERT(false);

		return;

	}



	master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor, scratch->mpc_info.mpc_factor, &scratch->pipe_pool, existing_state);

	master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor,

			scratch->mpc_info.mpc_factor, plane_index, &scratch->pipe_pool, existing_state);

	sort_pipes_for_splitting(&scratch->pipe_pool);



	for (odm_slice_index = 0; odm_slice_index < scratch->odm_info.odm_factor; odm_slice_index++) {
@@ -755,7 +765,7 @@ static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state 
		}

	}



	free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id);

	free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id, plane_index);

}



static unsigned int get_mpc_factor(struct dml2_context *ctx,
@@ -768,7 +778,7 @@ static unsigned int get_mpc_factor(struct dml2_context *ctx, 
	unsigned int plane_id;

	unsigned int cfg_idx;



	get_plane_id(state, status->plane_states[plane_idx], stream_id, &plane_id);

	get_plane_id(ctx, state, status->plane_states[plane_idx], stream_id, plane_idx, &plane_id);

	cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);

	if (ctx->architecture == dml2_architecture_20)

		return (unsigned int)disp_cfg->hw.DPPPerSurface[cfg_idx];
@@ -946,8 +956,8 @@ bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const s 


		for (plane_index = 0; plane_index < state->stream_status[stream_index].plane_count; plane_index++) {

			// Planes are ordered top to bottom.

			if (get_plane_id(state, state->stream_status[stream_index].plane_states[plane_index],

				stream_id, &plane_id)) {

			if (get_plane_id(ctx, state, state->stream_status[stream_index].plane_states[plane_index],

				stream_id, plane_index, &plane_id)) {

				plane_disp_cfg_index = find_disp_cfg_idx_by_plane_id(mapping, plane_id);



				// Setup mpc_info for this plane
@@ -971,7 +981,8 @@ bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const s 
				// Clear the pool assignment scratch (which is per plane)

				memset(&scratch.pipe_pool, 0, sizeof(struct dc_plane_pipe_pool));



				map_pipes_for_plane(ctx, state, state->streams[stream_index], state->stream_status[stream_index].plane_states[plane_index], &scratch, existing_state);

				map_pipes_for_plane(ctx, state, state->streams[stream_index],

					state->stream_status[stream_index].plane_states[plane_index], plane_index, &scratch, existing_state);

			} else {

				// Plane ID cannot be generated, therefore no DML mapping can be performed.

				ASSERT(false);

drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h

+3 −0
Original line number Diff line number Diff line
@@ -75,6 +75,8 @@ struct dml2_dml_to_dc_pipe_mapping { 
	bool dml_pipe_idx_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

	unsigned int dml_pipe_idx_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

	bool dml_pipe_idx_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

	unsigned int dml_pipe_idx_to_plane_index[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

	bool dml_pipe_idx_to_plane_index_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

};



struct dml2_wrapper_scratch {
@@ -96,6 +98,7 @@ struct dml2_wrapper_scratch { 


	struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;

	bool enable_flexible_pipe_mapping;

	bool plane_duplicate_exists;

};



struct dml2_helper_det_policy_scratch {

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+46 −8
Original line number Diff line number Diff line
@@ -931,10 +931,11 @@ static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml 
	return location;

}



static bool get_plane_id(const struct dc_state *context, const struct dc_plane_state *plane,

		unsigned int stream_id, unsigned int *plane_id)

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,

		unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)

{

	int i, j;

	bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;



	if (!plane_id)

		return false;
@@ -942,7 +943,8 @@ static bool get_plane_id(const struct dc_state *context, const struct dc_plane_s 
	for (i = 0; i < context->stream_count; i++) {

		if (context->streams[i]->stream_id == stream_id) {

			for (j = 0; j < context->stream_status[i].plane_count; j++) {

				if (context->stream_status[i].plane_states[j] == plane) {

				if (context->stream_status[i].plane_states[j] == plane &&

					(!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) {

					*plane_id = (i << 16) | j;

					return true;

				}
@@ -954,13 +956,13 @@ static bool get_plane_id(const struct dc_state *context, const struct dc_plane_s 
}



static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane,

		const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id)

		const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)

{

	unsigned int plane_id;

	int i = 0;

	int location = -1;



	if (!get_plane_id(context, plane, stream_id, &plane_id)) {

	if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {

		ASSERT(false);

		return -1;

	}
@@ -991,7 +993,41 @@ static void apply_legacy_svp_drr_settings(struct dml2_context *dml2, const struc 
	}

}



void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)

static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state)

{

	unsigned int i;

	unsigned int pipe_index = 0;

	unsigned int plane_index = 0;

	struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;



	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {

		dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false;

		dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[i] = 0;

	}



	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {

		struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];



		if (!pipe || !pipe->stream || !pipe->plane_state)

			continue;



		while (pipe) {

			pipe_index = pipe->pipe_idx;



			if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {

				dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index;

				plane_index++;

				dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true;

			}



			pipe = pipe->bottom_pipe;

		}



		plane_index = 0;

	}

}



void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)

{

	int i = 0, j = 0;

	int disp_cfg_stream_location, disp_cfg_plane_location;
@@ -1008,6 +1044,8 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct d 
	dml_dispcfg->plane.GPUVMMaxPageTableLevels = 4;

	dml_dispcfg->plane.HostVMEnable = false;



	dml2_populate_pipe_to_plane_index_mapping(dml2, context);



	for (i = 0; i < context->stream_count; i++) {

		disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg);
@@ -1044,7 +1082,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct d 
		} else {

			for (j = 0; j < context->stream_status[i].plane_count; j++) {

				disp_cfg_plane_location = map_plane_to_dml_display_cfg(dml2,

					context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id);

					context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j);



				if (disp_cfg_plane_location < 0)

					disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
@@ -1068,7 +1106,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct d 


				dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;



				if (get_plane_id(context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id,

				if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j,

					&dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))

					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, 
void dml2_translate_ip_params(const struct dc *in_dc, struct ip_params_st *out);

void dml2_translate_socbb_params(const struct dc *in_dc, struct soc_bounding_box_st *out);

void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states);

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg);

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg);

void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out);

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c

+11 −7
Original line number Diff line number Diff line
@@ -209,10 +209,11 @@ static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int 
	return -1;

}



static bool get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane,

	unsigned int stream_id, unsigned int *plane_id)

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,

	unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)

{

	int i, j;

	bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;



	if (!plane_id)

		return false;
@@ -220,7 +221,8 @@ static bool get_plane_id(const struct dc_state *state, const struct dc_plane_sta 
	for (i = 0; i < state->stream_count; i++) {

		if (state->streams[i]->stream_id == stream_id) {

			for (j = 0; j < state->stream_status[i].plane_count; j++) {

				if (state->stream_status[i].plane_states[j] == plane) {

				if (state->stream_status[i].plane_states[j] == plane &&

					(!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) {

					*plane_id = (i << 16) | j;

					return true;

				}
@@ -304,8 +306,9 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont 
		 * there is a need to know which DML pipe index maps to which DC pipe. The code below

		 * finds a dml_pipe_index from the plane id if a plane is valid. If a plane is not valid then

		 * it finds a dml_pipe_index from the stream id. */

		if (get_plane_id(context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

			context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id, &plane_id)) {

		if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

			context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id,

			in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

			dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);

		} else {

			dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);
@@ -445,8 +448,9 @@ bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc 
	for (i = 0; i < MAX_PIPES; i++) {

		if (!display_state->res_ctx.pipe_ctx[i].stream)

			continue;

		if (get_plane_id(display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

			display_state->res_ctx.pipe_ctx[i].stream->stream_id, &plane_id))

		if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

			display_state->res_ctx.pipe_ctx[i].stream->stream_id,

			in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

			dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);

		else

			dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state->res_ctx.pipe_ctx[i].stream->stream_id);