Commit 361600d1 authored by Benoît Monin's avatar Benoît Monin Committed by Thomas Bogendoerfer
Browse files

MIPS: Add Mobileye EyeQ6Lplus SoC dtsi 



Add the device tree include files for the EyeQ6Lplus system on chip
from Mobileye.

Those files provide the initial support of the SoC:
* The I6500 CPU and GIC interrupt controller.
* The OLB ("Other Logic Block") providing clocks, resets and pin controls.
* One UART.
* One GPIO controller.
* Two SPI controllers, one in host mode and one in target mode.
* One octoSPI flash controller.
* Two I2C controllers.

Signed-off-by: default avatarBenoît Monin <benoit.monin@bootlin.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 4eb9ed39

arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)



&olb {

	timer0_pins: timer0-pins {

		function = "timer0";

		pins = "PA0", "PA1";

	};

	timer1_pins: timer1-pins {

		function = "timer1";

		pins = "PA2", "PA3";

	};

	uart_ssi_pins: uart-ssi-pins {

		function = "uart_ssi";

		pins = "PA4", "PA5";

	};

	spi0_pins: spi0-pins {

		function = "spi0";

		pins = "PA6", "PA7", "PA8", "PA9";

	};

	uart0_pins: uart0-pins {

		function = "uart0";

		pins = "PA11", "PA12";

	};

	timer2_pins: timer2-pins {

		function = "timer2";

		pins = "PA13", "PA14";

	};

	timer3_pins: timer3-pins {

		function = "timer3";

		pins = "PA15", "PA16";

	};

	timer_ext0_pins: timer-ext0-pins {

		function = "timer_ext0";

		pins = "PA17", "PA18", "PA19", "PA20";

	};

	timer_ext0_input_a_pins: timer-ext0-input-a-pins {

		function = "timer_ext0";

		pins = "PA17";

	};

	pps0_pins: pps0-pins {

		function = "timer_ext0";

		pins = "PA17";

	};

	timer_ext0_input_b_pins: timer-ext0-input-b-pins {

		function = "timer_ext0";

		pins = "PA18";

	};

	timer_ext0_output_pins: timer-ext0-output-pins {

		function = "timer_ext0";

		pins = "PA19", "PA20";

	};

	spi1_pins: spi1-pins {

		function = "spi1";

		pins = "PA21", "PA22", "PA23", "PA24";

	};

	spi1_reduced_pins: spi1-reduced-pins {

		function = "spi1";

		pins = "PA21", "PA22", "PA23";

	};

	timer_ext1_pins: timer-ext1-pins {

		function = "timer_ext1";

		pins = "PA26", "PA27", "PA28", "PA29";

	};

	timer_ext1_input_a_pins: timer-ext1-input-a-pins {

		function = "timer_ext1";

		pins = "PA26";

	};

	timer_ext1_input_b_pins: timer-ext1-input-b-pins {

		function = "timer_ext1";

		pins = "PA27";

	};

	timer_ext1_output_pins: timer-ext1-output-pins {

		function = "timer_ext1";

		pins = "PA28", "PA29";

	};

	ext_ref_clk_pins: ext-ref-clk-pins {

		function = "ext_ref_clk";

		pins = "PA30";

	};

	mipi_ref_clk_pins: mipi-ref-clk-pins {

		function = "mipi_ref_clk";

		pins = "PA31";

	};

};

arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi

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// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

/*

 * Copyright 2025 Mobileye Vision Technologies Ltd.

 */



#include <dt-bindings/interrupt-controller/mips-gic.h>



#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>



/ {

	#address-cells = <2>;

	#size-cells = <2>;

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu@0 {

			device_type = "cpu";

			compatible = "img,i6500";

			reg = <0>;

			clocks = <&olb EQ6LPC_CPU_OCC>;

		};

	};



	cpu_intc: interrupt-controller {

		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;

		#address-cells = <0>;

		#interrupt-cells = <1>;

	};



	coherency-manager {

		compatible = "mobileye,eyeq6-cm";

	};



	xtal: clock-30000000 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		olb: system-controller@e8400000 {

			compatible = "mobileye,eyeq6lplus-olb", "syscon";

			reg = <0 0xe8400000 0x0 0x80000>;

			#reset-cells = <2>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		ospi: spi@e8800000 {

			compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0xe8800000 0x0 0x100000>,

			      <0 0xb0000000 0x0 0x30000000>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;

			cdns,fifo-depth = <128>;

			cdns,fifo-width = <4>;

			cdns,trigger-address = <0x00000000>;

			clocks  = <&olb EQ6LPC_PER_OSPI>;

			status = "disabled";

		};



		spi0: spi@eac0d000 {

			compatible = "snps,dw-apb-ssi";

			reg = <0 0xeac0d000 0x0 0x1000>;

			clocks = <&olb EQ6LPC_PER_SPI>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 11 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&olb 0 0>;

			reset-names = "spi";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		spi1: spi@eac0e000 {

			compatible = "snps,dw-apb-ssi";

			reg = <0 0xeac0e000 0x0 0x1000>;

			spi-slave;

			clocks = <&olb EQ6LPC_PER_SPI>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&olb 0 1>;

			reset-names = "spi";

			#address-cells = <0>;

			#size-cells = <0>;

			status = "disabled";

		};



		uart0: serial@eac10000 {

			compatible = "snps,dw-apb-uart";

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&olb EQ6LPC_PER_UART>;

			clock-frequency = <15625000>;

			reg = <0 0xeac10000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&olb 0 2>;

			status = "disabled";

		};



		i2c0: i2c@eac11000 {

			compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";

			reg = <0 0xeac11000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clock-frequency = <400000>;

			clocks = <&olb EQ6LPC_PER_I2C_SER>;

			resets = <&olb 0 3>;

			i2c-sda-hold-time-ns = <50>;

			status = "disabled";

		};



		i2c1: i2c@eac12000 {

			compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";

			reg = <0 0xeac12000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;

			clock-frequency = <400000>;

			clocks = <&olb EQ6LPC_PER_I2C_SER>;

			resets = <&olb 0 4>;

			i2c-sda-hold-time-ns = <50>;

			status = "disabled";

		};



		gpio: gpio@eac14000 {

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0xeac14000 0x0 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&olb 0 13>;

			porta: gpio-port@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				gpio-ranges = <&olb 0 0 32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupt-parent = <&gic>;

				interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		gic: interrupt-controller@f0920000 {

			compatible = "mti,gic";

			reg = <0x0 0xf0920000 0x0 0x20000>;

			interrupt-controller;

			#interrupt-cells = <3>;

			interrupt-parent = <&cpu_intc>;

			timer {

				compatible = "mti,gic-timer";

				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

				clocks = <&olb EQ6LPC_CPU_OCC>;

			};

		};

	};

};



#include "eyeq6lplus-pins.dtsi"