Commit 36304006 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'loongarch-6.12' of... 

Merge tag 'loongarch-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch updates from Huacai Chen:

 - Fix objtool about do_syscall() and Clang

 - Enable generic CPU vulnerabilites support

 - Enable ACPI BGRT handling

 - Rework CPU feature probe from CPUCFG/IOCSR

 - Add ARCH_HAS_SET_MEMORY support

 - Add ARCH_HAS_SET_DIRECT_MAP support

 - Improve hardware page table walker

 - Simplify _percpu_read() and _percpu_write()

 - Add advanced extended IRQ model documentions

 - Some bug fixes and other small changes

* tag 'loongarch-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
  Docs/LoongArch: Add advanced extended IRQ model description
  LoongArch: Remove posix_types.h include from sigcontext.h
  LoongArch: Fix memleak in pci_acpi_scan_root()
  LoongArch: Simplify _percpu_read() and _percpu_write()
  LoongArch: Improve hardware page table walker
  LoongArch: Add ARCH_HAS_SET_DIRECT_MAP support
  LoongArch: Add ARCH_HAS_SET_MEMORY support
  LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
  LoongArch: Enable ACPI BGRT handling
  LoongArch: Enable generic CPU vulnerabilites support
  LoongArch: Remove STACK_FRAME_NON_STANDARD(do_syscall)
  LoongArch: Set AS_HAS_THIN_ADD_SUB as y if AS_IS_LLVM
  LoongArch: Enable objtool for Clang
  objtool: Handle frame pointer related instructions
parents ec384984 f339bd3b

Documentation/arch/loongarch/irq-chip-model.rst

+32 −0
Original line number Diff line number Diff line
@@ -85,6 +85,38 @@ to CPUINTC directly:: 
    | Devices |

    +---------+



Advanced Extended IRQ model

===========================



In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go

to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go

to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts

go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::



 +-----+     +-----------------------+     +-------+

 | IPI | --> |        CPUINTC        | <-- | Timer |

 +-----+     +-----------------------+     +-------+

              ^          ^          ^

              |          |          |

       +---------+ +----------+ +---------+     +-------+

       | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |

       +---------+ +----------+ +---------+     +-------+

            ^            ^

            |            |

       +---------+  +---------+

       | PCH-PIC |  | PCH-MSI |

       +---------+  +---------+

         ^     ^           ^

         |     |           |

 +---------+ +---------+ +---------+

 | Devices | | PCH-LPC | | Devices |

 +---------+ +---------+ +---------+

                  ^

                  |

             +---------+

             | Devices |

             +---------+



ACPI-related definitions

========================

Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst

+32 −0
Original line number Diff line number Diff line
@@ -87,6 +87,38 @@ PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC:: 
    | Devices |

    +---------+



高级扩展IRQ模型

===============



在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，

CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC，而后通过AVECINTC直接

送达CPUINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC

统一收集，再直接到达CPUINTC::



 +-----+     +-----------------------+     +-------+

 | IPI | --> |        CPUINTC        | <-- | Timer |

 +-----+     +-----------------------+     +-------+

              ^          ^          ^

              |          |          |

       +---------+ +----------+ +---------+     +-------+

       | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |

       +---------+ +----------+ +---------+     +-------+

            ^            ^

            |            |

       +---------+  +---------+

       | PCH-PIC |  | PCH-MSI |

       +---------+  +---------+

         ^     ^           ^

         |     |           |

 +---------+ +---------+ +---------+

 | Devices | | PCH-LPC | | Devices |

 +---------+ +---------+ +---------+

                  ^

                  |

             +---------+

             | Devices |

             +---------+



ACPI相关的定义

==============

arch/loongarch/Kconfig

+5 −2
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ config LOONGARCH 
	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE

	select ARCH_HAS_PTE_DEVMAP

	select ARCH_HAS_PTE_SPECIAL

	select ARCH_HAS_SET_MEMORY

	select ARCH_HAS_SET_DIRECT_MAP

	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST

	select ARCH_INLINE_READ_LOCK if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
@@ -82,6 +84,7 @@ config LOONGARCH 
	select GENERIC_CMOS_UPDATE

	select GENERIC_CPU_AUTOPROBE

	select GENERIC_CPU_DEVICES

	select GENERIC_CPU_VULNERABILITIES

	select GENERIC_ENTRY

	select GENERIC_GETTIMEOFDAY

	select GENERIC_IOREMAP if !ARCH_IOREMAP
@@ -147,7 +150,7 @@ config LOONGARCH 
	select HAVE_LIVEPATCH

	select HAVE_MOD_ARCH_SPECIFIC

	select HAVE_NMI

	select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB && !CC_IS_CLANG

	select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB

	select HAVE_PCI

	select HAVE_PERF_EVENTS

	select HAVE_PERF_REGS
@@ -267,7 +270,7 @@ config AS_HAS_FCSR_CLASS 
	def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)



config AS_HAS_THIN_ADD_SUB

	def_bool $(cc-option,-Wa$(comma)-mthin-add-sub)

	def_bool $(cc-option,-Wa$(comma)-mthin-add-sub) || AS_IS_LLVM



config AS_HAS_LSX_EXTENSION

	def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0)

arch/loongarch/include/asm/atomic.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#define __LL		"ll.w	"

#define __SC		"sc.w	"

#define __AMADD		"amadd.w	"

#define __AMOR		"amor.w		"

#define __AMAND_DB	"amand_db.w	"

#define __AMOR_DB	"amor_db.w	"

#define __AMXOR_DB	"amxor_db.w	"
@@ -22,6 +23,7 @@ 
#define __LL		"ll.d	"

#define __SC		"sc.d	"

#define __AMADD		"amadd.d	"

#define __AMOR		"amor.d		"

#define __AMAND_DB	"amand_db.d	"

#define __AMOR_DB	"amor_db.d	"

#define __AMXOR_DB	"amxor_db.d	"

arch/loongarch/include/asm/cpu-features.h

+2 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
#define cpu_has_lbt_mips	cpu_opt(LOONGARCH_CPU_LBT_MIPS)

#define cpu_has_lbt		(cpu_has_lbt_x86|cpu_has_lbt_arm|cpu_has_lbt_mips)

#define cpu_has_csr		cpu_opt(LOONGARCH_CPU_CSR)

#define cpu_has_iocsr		cpu_opt(LOONGARCH_CPU_IOCSR)

#define cpu_has_tlb		cpu_opt(LOONGARCH_CPU_TLB)

#define cpu_has_watch		cpu_opt(LOONGARCH_CPU_WATCH)

#define cpu_has_vint		cpu_opt(LOONGARCH_CPU_VINT)
@@ -65,6 +66,7 @@ 
#define cpu_has_guestid		cpu_opt(LOONGARCH_CPU_GUESTID)

#define cpu_has_hypervisor	cpu_opt(LOONGARCH_CPU_HYPERVISOR)

#define cpu_has_ptw		cpu_opt(LOONGARCH_CPU_PTW)

#define cpu_has_lspw		cpu_opt(LOONGARCH_CPU_LSPW)

#define cpu_has_avecint		cpu_opt(LOONGARCH_CPU_AVECINT)



#endif /* __ASM_CPU_FEATURES_H */