Commit 3664282f authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

clk: qcom: x1e80100-dispcc: Add USB4 router link resets 



The router link clock branches also feature some reset logic, which is
required to properly power sequence the hardware for DP tunneling over
USB4.

Describe these missing resets.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-topic-usb4_x1e_dispcc-v1-2-14c68d842c71@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent c84b824d

drivers/clk/qcom/dispcc-x1e80100.c

+3 −0
Original line number Diff line number Diff line
@@ -1618,6 +1618,9 @@ static struct clk_regmap *disp_cc_x1e80100_clocks[] = { 


static const struct qcom_reset_map disp_cc_x1e80100_resets[] = {

	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },

	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8044, .bit = 2 },

	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8068, .bit = 2 },

	[DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8088, .bit = 2 },

	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },

	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },

};