Unverified Commit 368546eb authored by Samuel Holland's avatar Samuel Holland Committed by Palmer Dabbelt
Browse files

riscv: Call riscv_user_isa_enable() only on the boot hart 



Now that the [ms]envcfg CSR value is maintained per thread, not per
hart, riscv_user_isa_enable() only needs to be called once during boot,
to set the value for the init task. This also allows it to be marked as
__init.

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarDeepak Gupta <debug@rivosinc.com>
Signed-off-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240814081126.956287-4-samuel.holland@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 5fc7355f

arch/riscv/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); 
/* Per-cpu ISA extensions. */

extern struct riscv_isainfo hart_isa[NR_CPUS];



void riscv_user_isa_enable(void);

void __init riscv_user_isa_enable(void);



#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) {	\

	.name = #_name,									\

arch/riscv/kernel/cpufeature.c

+2 −2
Original line number Diff line number Diff line
@@ -920,12 +920,12 @@ unsigned long riscv_get_elf_hwcap(void) 
	return hwcap;

}



void riscv_user_isa_enable(void)

void __init riscv_user_isa_enable(void)

{

	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))

		current->thread.envcfg |= ENVCFG_CBZE;

	else if (any_cpu_has_zicboz)

		pr_warn_once("Zicboz disabled as it is unavailable on some harts\n");

		pr_warn("Zicboz disabled as it is unavailable on some harts\n");

}



#ifdef CONFIG_RISCV_ALTERNATIVE

arch/riscv/kernel/smpboot.c

+0 −2
Original line number Diff line number Diff line
@@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void) 
	numa_add_cpu(curr_cpuid);

	set_cpu_online(curr_cpuid, true);



	riscv_user_isa_enable();



	/*

	 * Remote cache and TLB flushes are ignored while the CPU is offline,

	 * so flush them both right now just in case.