Unverified Commit 36904926 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Palmer Dabbelt
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riscv: errata: thead: use pa based instructions for CMO 



T-HEAD CPUs such as C906/C910/C920 support phy address based CMO, use
them so that we don't need to convert to virt address.

Signed-off-by: default avatarJisheng Zhang <jszhang@kernel.org>
Reviewed-by: default avatarGuo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20231114143338.2406-3-jszhang@kernel.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent a4ff64ed

arch/riscv/errata/thead/errata.c

+6 −12
Original line number Diff line number Diff line
@@ -58,9 +58,9 @@ static bool errata_probe_pbmt(unsigned int stage, 
 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |

 *   0000000    11001     00000      000      00000  0001011

 */

#define THEAD_INVAL_A0	".long 0x0265000b"

#define THEAD_CLEAN_A0	".long 0x0255000b"

#define THEAD_FLUSH_A0	".long 0x0275000b"

#define THEAD_INVAL_A0	".long 0x02a5000b"

#define THEAD_CLEAN_A0	".long 0x0295000b"

#define THEAD_FLUSH_A0	".long 0x02b5000b"

#define THEAD_SYNC_S	".long 0x0190000b"



#define THEAD_CMO_OP(_op, _start, _size, _cachesize)			\
@@ -79,23 +79,17 @@ asm volatile("mv a0, %1\n\t" \ 


static void thead_errata_cache_inv(phys_addr_t paddr, size_t size)

{

	void *vaddr = phys_to_virt(paddr);



	THEAD_CMO_OP(INVAL, vaddr, size, riscv_cbom_block_size);

	THEAD_CMO_OP(INVAL, paddr, size, riscv_cbom_block_size);

}



static void thead_errata_cache_wback(phys_addr_t paddr, size_t size)

{

	void *vaddr = phys_to_virt(paddr);



	THEAD_CMO_OP(CLEAN, vaddr, size, riscv_cbom_block_size);

	THEAD_CMO_OP(CLEAN, paddr, size, riscv_cbom_block_size);

}



static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size)

{

	void *vaddr = phys_to_virt(paddr);



	THEAD_CMO_OP(FLUSH, vaddr, size, riscv_cbom_block_size);

	THEAD_CMO_OP(FLUSH, paddr, size, riscv_cbom_block_size);

}



static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops = {