Commit 36a02456 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Use get_smn_base in aqua_vanjaram 



Use get_smn_base interface to get IP die instance's base offset in
aqua_vanjaram. encode_ext_smn_addressing is not used.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 467ebfe6

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+4 −3
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
 *

 *

 */

#include "amdgpu_reg_access.h"

#include <linux/debugfs.h>

#include <linux/list.h>

#include <linux/module.h>
@@ -5535,11 +5536,11 @@ static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev, 
	 * is changed. In such case, replace the aqua_vanjaram implementation

	 * with more common helper */

	reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +

		   aqua_vanjaram_encode_ext_smn_addressing(instance);

		   amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);

	fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr);



	reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) +

		   aqua_vanjaram_encode_ext_smn_addressing(instance);

		   amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);

	boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr);



	socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
@@ -5605,7 +5606,7 @@ static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev, 
	int retry_loop;



	reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +

		   aqua_vanjaram_encode_ext_smn_addressing(instance);

		   amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);



	for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {

		reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

+55 −1
Original line number Diff line number Diff line
@@ -283,17 +283,71 @@ void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 
	adev->reg.pcie.port_wreg(adev, reg, v);

}



static int amdgpu_reg_get_smn_base_version(struct amdgpu_device *adev)

{

	struct pci_dev *pdev = adev->pdev;

	int id;



	if (amdgpu_sriov_vf(adev))

		return -EOPNOTSUPP;



	id = (pdev->device >> 4) & 0xFFFF;

	if (id == 0x74A || id == 0x74B || id == 0x75A || id == 0x75B)

		return 1;



	return -EOPNOTSUPP;

}



uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev,

				   enum amd_hw_ip_block_type block,

				   int die_inst)

{

	if (!adev->reg.smn.get_smn_base) {

		dev_err_once(adev->dev, "SMN base address callback not set\n");

		int version = amdgpu_reg_get_smn_base_version(adev);

		switch (version) {

		case 1:

			return amdgpu_reg_smn_v1_0_get_base(adev, block,

							    die_inst);

		default:

			dev_err_once(

				adev->dev,

				"SMN base address query not supported for this device\n");

			return 0;

		}

		return 0;

	}

	return adev->reg.smn.get_smn_base(adev, block, die_inst);

}



uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev,

				      enum amd_hw_ip_block_type block,

				      int die_inst)

{

	uint64_t smn_base;



	if (die_inst == 0)

		return 0;



	switch (block) {

	case XGMI_HWIP:

	case NBIO_HWIP:

	case MP0_HWIP:

	case UMC_HWIP:

	case DF_HWIP:

		smn_base = ((uint64_t)(die_inst & 0x3) << 32) | (1ULL << 34);

		break;

	default:

		dev_warn_once(

			adev->dev,

			"SMN base address query not supported for this block %d\n",

			block);

		smn_base = 0;

		break;

	}



	return smn_base;

}



/*

 * register access helper functions.

 */

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

+3 −0
Original line number Diff line number Diff line
@@ -122,6 +122,9 @@ void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, 
uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev,

				   enum amd_hw_ip_block_type block,

				   int die_inst);

uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev,

				      enum amd_hw_ip_block_type block,

				      int die_inst);



uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,

			    uint32_t acc_flags);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

+8 −4
Original line number Diff line number Diff line
@@ -338,7 +338,7 @@ static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link 
	if (!(adev->aid_mask & BIT(i)))

		return U32_MAX;



	addr += adev->asic_funcs->encode_ext_smn_addressing(i);

	addr += amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i);



	return RREG32_PCIE_EXT(addr);

}
@@ -1293,7 +1293,10 @@ static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev) 


static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base)

{

	WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL);

	uint64_t smn_base =

		amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst);



	WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL);

}



static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst)
@@ -1503,6 +1506,7 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a 
					    u64 mca_base, struct ras_err_data *err_data)

{

	int xgmi_inst = mcm_info->die_id;

	uint64_t smn_base;

	u64 status = 0;



	status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS);
@@ -1519,8 +1523,8 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a 
	default:

		break;

	}



	WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL);

	smn_base = amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst);

	WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL);

}



static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data)

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

+1 −20
Original line number Diff line number Diff line
@@ -58,25 +58,6 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) 
	adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;

}



/* Fixed pattern for smn addressing on different AIDs:

 *   bit[34]: indicate cross AID access

 *   bit[33:32]: indicate target AID id

 * AID id range is 0 ~ 3 as maximum AID number is 4.

 */

u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id)

{

	u64 ext_offset;



	/* local routing and bit[34:32] will be zeros */

	if (ext_id == 0)

		return 0;



	/* Initiated from host, accessing to all non-zero aids are cross traffic */

	ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34);



	return ext_offset;

}



static enum amdgpu_gfx_partition

__aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr)

{
@@ -590,7 +571,7 @@ static void aqua_read_smn_ext(struct amdgpu_device *adev, 
			      uint64_t smn_addr, int i)

{

	regdata->addr =

		smn_addr + adev->asic_funcs->encode_ext_smn_addressing(i);

		smn_addr + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i);

	regdata->value = RREG32_PCIE_EXT(regdata->addr);

}