Commit 36b98a72 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
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drm/amd/pm: Add generic pcie dpm table



Add a generic pcie dpm table which contains the number of link clock
levels and link clock, pcie gen speed/width corresponding to each level.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b4742a9e
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+9 −0
Original line number Diff line number Diff line
@@ -314,6 +314,15 @@ struct smu_dpm_table {
#define SMU_DPM_TABLE_MAX(table) \
	((table)->count > 0 ? (table)->dpm_levels[(table)->count - 1].value : 0)

#define SMU_MAX_PCIE_LEVELS 3

struct smu_pcie_table {
	uint8_t pcie_gen[SMU_MAX_PCIE_LEVELS];
	uint8_t pcie_lane[SMU_MAX_PCIE_LEVELS];
	uint16_t lclk_freq[SMU_MAX_PCIE_LEVELS];
	uint32_t lclk_levels;
};

struct smu_bios_boot_up_values {
	uint32_t			revision;
	uint32_t			gfxclk;