Commit 36cab4bd authored by Benoît Monin's avatar Benoît Monin Committed by Thomas Bogendoerfer
Browse files

reset: eyeq: Add Mobileye EyeQ6Lplus OLB 



Declare the two reset domains found in the EyeQ6Lplus OLB and add
them to the data matched by 'mobileye,eyeq6lplus-olb' compatible.

Those reset domains are identical to those present in the EyeQ5
OLB, so no changes are needed to support them.

Also select reset-eyeq for all EYEQ SoCs instead of listing each one
individually, as it is needed by all Mobileye EyeQ SoC.

Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarBenoît Monin <benoit.monin@bootlin.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 2aca86de

drivers/reset/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -85,9 +85,9 @@ config RESET_EIC7700 


config RESET_EYEQ

	bool "Mobileye EyeQ reset controller"

	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST

	depends on EYEQ || COMPILE_TEST

	select AUXILIARY_BUS

	default MACH_EYEQ5 || MACH_EYEQ6H

	default EYEQ

	help

	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L

	  and EyeQ6H SoCs.

drivers/reset/reset-eyeq.c

+31 −0
Original line number Diff line number Diff line
@@ -49,6 +49,18 @@ 
 *  8. MPC0	 9. MPC1	10. MPC2	11. MPC3

 * 12. MPC4

 *

 * Known resets in EyeQ6Lplus domain 0 (type EQR_EYEQ5_PCIE):

 *  0. SPI0	 1. SPI1	 2. UART0	 3. I2C0

 *  4. I2C1	 5. TIMER0	 6. TIMER1	 7. TIMER2

 *  8. TIMER3	 9. WD0		10. WD1		11. EXT0

 * 12. EXT1	13. GPIO

 *

 * Known resets in EyeQ6Lplus domain 1 (type EQR_EYEQ5_ACRP):

 *  0. VMP0	 1. VMP1	 2. VMP2	 3. VMP3

 *  4. PMA0	 5. PMA1	 6. PMAC0	 7. PMAC1

 *  8. MPC0	 9. MPC1	10. MPC2	11. MPC3

 * 12. MPC4

 *

 * Known resets in EyeQ6H west/east (type EQR_EYEQ6H_SARCR):

 *  0. CAN	 1. SPI0	 2. SPI1	 3. UART0

 *  4. UART1	 5. I2C0	 6. I2C1	 7. -hole-
@@ -521,6 +533,24 @@ static const struct eqr_match_data eqr_eyeq6l_data = { 
	.domains	= eqr_eyeq6l_domains,

};



static const struct eqr_domain_descriptor eqr_eyeq6lplus_domains[] = {

	{

		.type = EQR_EYEQ5_PCIE,

		.valid_mask = 0x3FFF,

		.offset = 0x004,

	},

	{

		.type = EQR_EYEQ5_ACRP,

		.valid_mask = 0x00FF,

		.offset = 0x200,

	},

};



static const struct eqr_match_data eqr_eyeq6lplus_data = {

	.domain_count	= ARRAY_SIZE(eqr_eyeq6lplus_domains),

	.domains	= eqr_eyeq6lplus_domains,

};



/* West and east OLBs each have an instance. */

static const struct eqr_domain_descriptor eqr_eyeq6h_we_domains[] = {

	{
@@ -555,6 +585,7 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = { 
static const struct of_device_id eqr_match_table[] = {

	{ .compatible = "mobileye,eyeq5-olb", .data = &eqr_eyeq5_data },

	{ .compatible = "mobileye,eyeq6l-olb", .data = &eqr_eyeq6l_data },

	{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eqr_eyeq6lplus_data },

	{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },

	{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },

	{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },