Commit 3706f141 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'bnxt_en-support-new-5760x-p7-devices' 

Michael Chan says:

====================
bnxt_en: Support new 5760X P7 devices

This series completes the basic support for the new 5760X P7 devices
with new PCI IDs added in the last patch.

Thie first patch fixes a backing store issue introduced in the last
patchset last week.  The 2nd patch is the new firmware interface
required to support the new chips.  The next few patches are doorbell
changes, refactoring, and new hardware interface structures.  New
changes to support packet reception including TPA are added in patch 10.
The next 4 patches are ethernet link related changes to support the
new chip.
====================

Link: https://lore.kernel.org/r/20231201223924.26955-1-michael.chan@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 91051f00 2012a6ab

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+297 −86

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/broadcom/bnxt/bnxt.h

+174 −15
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
 */

#define DRV_VER_MAJ	1

#define DRV_VER_MIN	10

#define DRV_VER_UPD	2

#define DRV_VER_UPD	3



#include <linux/ethtool.h>

#include <linux/interrupt.h>
@@ -139,11 +139,15 @@ struct tx_cmp { 
	__le32 tx_cmp_flags_type;

	#define CMP_TYPE					(0x3f << 0)

	 #define CMP_TYPE_TX_L2_CMP				 0

	 #define CMP_TYPE_TX_L2_COAL_CMP			 2

	 #define CMP_TYPE_TX_L2_PKT_TS_CMP			 4

	 #define CMP_TYPE_RX_L2_CMP				 17

	 #define CMP_TYPE_RX_AGG_CMP				 18

	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19

	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21

	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22

	 #define CMP_TYPE_RX_L2_V3_CMP				 23

	 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP		 25

	 #define CMP_TYPE_STATUS_CMP				 32

	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34

	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36
@@ -170,9 +174,13 @@ struct tx_cmp { 
	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)

	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)



	__le32 tx_cmp_unsed_3;

	__le32 sq_cons_idx;

	#define TX_CMP_SQ_CONS_IDX_MASK				0x00ffffff

};



#define TX_CMP_SQ_CONS_IDX(txcmp)					\

	(le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)



struct rx_cmp {

	__le32 rx_cmp_len_flags_type;

	#define RX_CMP_CMP_TYPE					(0x3f << 0)
@@ -200,8 +208,20 @@ struct rx_cmp { 
	 #define RX_CMP_AGG_BUFS_SHIFT				 1

	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)

	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9

	#define RX_CMP_V3_RSS_EXT_OP_LEGACY			(0xf << 12)

	 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT		 12

	#define RX_CMP_V3_RSS_EXT_OP_NEW			(0xf << 8)

	 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT			 8

	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)

	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16

	#define RX_CMP_SUB_NS_TS				(0xf << 16)

	 #define RX_CMP_SUB_NS_TS_SHIFT				 16

	#define RX_CMP_METADATA1				(0xf << 28)

	 #define RX_CMP_METADATA1_SHIFT				 28

	#define RX_CMP_METADATA1_TPID_SEL			(0x7 << 28)

	#define RX_CMP_METADATA1_TPID_8021Q			(0x1 << 28)

	#define RX_CMP_METADATA1_TPID_8021AD			(0x0 << 28)

	#define RX_CMP_METADATA1_VALID				(0x8 << 28)



	__le32 rx_cmp_rss_hash;

};
@@ -215,6 +235,30 @@ struct rx_cmp { 
	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\

	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)



#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp)				\

	((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\

	 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)



#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp)				\

	((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\

	 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)



#define RX_CMP_V3_HASH_TYPE(bp, rxcmp)				\

	(((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ?		\

	  RX_CMP_V3_HASH_TYPE_NEW(rxcmp) :			\

	  RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))



#define EXT_OP_INNER_4		0x0

#define EXT_OP_OUTER_4		0x2

#define EXT_OP_INNFL_3		0x8

#define EXT_OP_OUTFL_3		0xa



#define RX_CMP_VLAN_VALID(rxcmp)				\

	((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))



#define RX_CMP_VLAN_TPID_SEL(rxcmp)				\

	(le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)



struct rx_cmp_ext {

	__le32 rx_cmp_flags2;

	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1
@@ -262,6 +306,9 @@ struct rx_cmp_ext { 


	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)

	 #define RX_CMPL_CFA_CODE_SFT				 16

	#define RX_CMPL_METADATA0_TCI_MASK			(0xffff << 16)

	#define RX_CMPL_METADATA0_VID_MASK			(0x0fff << 16)

	 #define RX_CMPL_METADATA0_SFT				 16



	__le32 rx_cmp_timestamp;

};
@@ -287,6 +334,10 @@ struct rx_cmp_ext { 
	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\

	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)



#define RX_CMP_METADATA0_TCI(rxcmp1)					\

	((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) &		\

	  RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)



struct rx_agg_cmp {

	__le32 rx_agg_cmp_len_flags_type;

	#define RX_AGG_CMP_TYPE					(0x3f << 0)
@@ -329,10 +380,18 @@ struct rx_tpa_start_cmp { 
	#define RX_TPA_START_CMP_V1				(0x1 << 0)

	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)

	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9

	#define RX_TPA_START_CMP_V3_RSS_HASH_TYPE		(0x1ff << 7)

	 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT	 7

	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)

	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25

	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)

	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16

	#define RX_TPA_START_CMP_METADATA1			(0xf << 28)

	 #define RX_TPA_START_CMP_METADATA1_SHIFT		 28

	#define RX_TPA_START_METADATA1_TPID_SEL			(0x7 << 28)

	#define RX_TPA_START_METADATA1_TPID_8021Q		(0x1 << 28)

	#define RX_TPA_START_METADATA1_TPID_8021AD		(0x0 << 28)

	#define RX_TPA_START_METADATA1_VALID			(0x8 << 28)



	__le32 rx_tpa_start_cmp_rss_hash;

};
@@ -346,6 +405,11 @@ struct rx_tpa_start_cmp { 
	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\

	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)



#define TPA_START_V3_HASH_TYPE(rx_tpa_start)				\

	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\

	   RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >>			\

	  RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)



#define TPA_START_AGG_ID(rx_tpa_start)					\

	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\

	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
@@ -358,6 +422,14 @@ struct rx_tpa_start_cmp { 
	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\

	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))



#define TPA_START_VLAN_VALID(rx_tpa_start)				\

	((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 &			\

	 cpu_to_le32(RX_TPA_START_METADATA1_VALID))



#define TPA_START_VLAN_TPID_SEL(rx_tpa_start)				\

	(le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\

	 RX_TPA_START_METADATA1_TPID_SEL)



struct rx_tpa_start_cmp_ext {

	__le32 rx_tpa_start_cmp_flags2;

	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)
@@ -368,6 +440,8 @@ struct rx_tpa_start_cmp_ext { 
	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)

	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)

	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10

	#define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE		(0x1 << 10)

	#define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO		(0x1 << 11)

	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)

	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16
@@ -381,6 +455,9 @@ struct rx_tpa_start_cmp_ext { 
	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)

	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)

	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16

	#define RX_TPA_START_CMP_METADATA0_TCI_MASK		(0xffff << 16)

	#define RX_TPA_START_CMP_METADATA0_VID_MASK		(0x0fff << 16)

	 #define RX_TPA_START_CMP_METADATA0_SFT			 16

	__le32 rx_tpa_start_cmp_hdr_info;

};
@@ -397,6 +474,11 @@ struct rx_tpa_start_cmp_ext { 
	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\

	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)



#define TPA_START_METADATA0_TCI(rx_tpa_start)				\

	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\

	  RX_TPA_START_CMP_METADATA0_TCI_MASK) >>			\

	 RX_TPA_START_CMP_METADATA0_SFT)



struct rx_tpa_end_cmp {

	__le32 rx_tpa_end_cmp_len_flags_type;

	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)
@@ -541,6 +623,8 @@ struct nqe_cn { 
	#define NQ_CN_TYPE_SFT            0

	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL

	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION

	#define NQ_CN_TOGGLE_MASK         0xc0UL

	#define NQ_CN_TOGGLE_SFT          6

	__le16	reserved16;

	__le32	cq_handle_low;

	__le32	v;
@@ -561,6 +645,10 @@ struct nqe_cn { 
#define BNXT_SET_NQ_HDL(cpr)						\

	(((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)



#define NQE_CN_TYPE(type)	((type) & NQ_CN_TYPE_MASK)

#define NQE_CN_TOGGLE(type)	(((type) & NQ_CN_TOGGLE_MASK) >>	\

				 NQ_CN_TOGGLE_SFT)



#define DB_IDX_MASK						0xffffff

#define DB_IDX_VALID						(0x1 << 26)

#define DB_IRQ_DIS						(0x1 << 27)
@@ -576,9 +664,14 @@ struct nqe_cn { 


/* 64-bit doorbell */

#define DBR_INDEX_MASK					0x0000000000ffffffULL

#define DBR_EPOCH_MASK					0x01000000UL

#define DBR_EPOCH_SFT					24

#define DBR_TOGGLE_MASK					0x06000000UL

#define DBR_TOGGLE_SFT					25

#define DBR_XID_MASK					0x000fffff00000000ULL

#define DBR_XID_SFT					32

#define DBR_PATH_L2					(0x1ULL << 56)

#define DBR_VALID					(0x1ULL << 58)

#define DBR_TYPE_SQ					(0x0ULL << 60)

#define DBR_TYPE_RQ					(0x1ULL << 60)

#define DBR_TYPE_SRQ					(0x2ULL << 60)
@@ -591,6 +684,7 @@ struct nqe_cn { 
#define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)

#define DBR_TYPE_NQ					(0xaULL << 60)

#define DBR_TYPE_NQ_ARM					(0xbULL << 60)

#define DBR_TYPE_NQ_MASK				(0xeULL << 60)

#define DBR_TYPE_NULL					(0xfULL << 60)



#define DB_PF_OFFSET_P5					0x10000
@@ -819,9 +913,17 @@ struct bnxt_db_info { 
		u32		db_key32;

	};

	u32			db_ring_mask;

	u32			db_epoch_mask;

	u8			db_epoch_shift;

};



#define DB_RING_IDX(db, idx)	((idx) & (db)->db_ring_mask)

#define DB_EPOCH(db, idx)	(((idx) & (db)->db_epoch_mask) <<	\

				 ((db)->db_epoch_shift))



#define DB_TOGGLE(tgl)		((tgl) << DBR_TOGGLE_SFT)



#define DB_RING_IDX(db, idx)	(((idx) & (db)->db_ring_mask) |		\

				 DB_EPOCH(db, idx))



struct bnxt_tx_ring_info {

	struct bnxt_napi	*bnapi;
@@ -925,6 +1027,8 @@ struct bnxt_tpa_info { 


	u16			cfa_code; /* cfa_code in TPA start compl */

	u8			agg_count;

	u8			vlan_valid:1;

	u8			cfa_code_valid:1;

	struct rx_agg_cmp	*agg_arr;

};
@@ -1018,6 +1122,7 @@ struct bnxt_cp_ring_info { 
	u8			had_work_done:1;

	u8			has_more_work:1;

	u8			had_nqe_notify:1;

	u8			toggle;



	u8			cp_ring_type;

	u8			cp_idx;
@@ -1255,6 +1360,7 @@ struct bnxt_link_info { 
#define BNXT_LINK_STATE_DOWN	1

#define BNXT_LINK_STATE_UP	2

#define BNXT_LINK_IS_UP(bp)	((bp)->link_info.link_state == BNXT_LINK_STATE_UP)

	u8			active_lanes;

	u8			duplex;

#define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF

#define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
@@ -1289,8 +1395,11 @@ struct bnxt_link_info { 
#define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB

#define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB

#define BNXT_LINK_SPEED_200GB	PORT_PHY_QCFG_RESP_LINK_SPEED_200GB

#define BNXT_LINK_SPEED_400GB	PORT_PHY_QCFG_RESP_LINK_SPEED_400GB

	u16			support_speeds;

	u16			support_pam4_speeds;

	u16			support_speeds2;



	u16			auto_link_speeds;	/* fw adv setting */

#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB

#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
@@ -1306,12 +1415,52 @@ struct bnxt_link_info { 
#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G

#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G

#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G

	u16			auto_link_speeds2;

#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB

#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB

#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB

#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB

#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB

#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB

#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56

#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56

#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56

#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56

#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112

#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112

#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112	\

	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112



	u16			support_auto_speeds;

	u16			support_pam4_auto_speeds;

	u16			support_auto_speeds2;



	u16			lp_auto_link_speeds;

	u16			lp_auto_pam4_link_speeds;

	u16			force_link_speed;

	u16			force_pam4_link_speed;

	u16			force_link_speed2;

#define BNXT_LINK_SPEED_50GB_PAM4	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56

#define BNXT_LINK_SPEED_100GB_PAM4	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56

#define BNXT_LINK_SPEED_200GB_PAM4	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56

#define BNXT_LINK_SPEED_400GB_PAM4	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56

#define BNXT_LINK_SPEED_100GB_PAM4_112	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112

#define BNXT_LINK_SPEED_200GB_PAM4_112	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112

#define BNXT_LINK_SPEED_400GB_PAM4_112	\

	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112



	u32			preemphasis;

	u8			module_status;

	u8			active_fec_sig_mode;
@@ -1342,6 +1491,7 @@ struct bnxt_link_info { 
	u8			req_signal_mode;

#define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ

#define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4

#define BNXT_SIG_MODE_PAM4_112	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112

#define BNXT_SIG_MODE_MAX	(PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)

	u8			req_duplex;

	u8			req_flow_ctrl;
@@ -1611,6 +1761,7 @@ struct bnxt_ctx_mem_type { 
#define BNXT_CTX_XPAR	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION



#define BNXT_CTX_MAX	(BNXT_CTX_TIM + 1)

#define BNXT_CTX_L2_MAX	(BNXT_CTX_FTQM + 1)

#define BNXT_CTX_V2_MAX	(BNXT_CTX_XPAR + 1)

#define BNXT_CTX_INV	((u16)-1)
@@ -1755,6 +1906,10 @@ enum board_idx { 
	BCM57508_NPAR,

	BCM57504_NPAR,

	BCM57502_NPAR,

	BCM57608,

	BCM57604,

	BCM57602,

	BCM57601,

	BCM58802,

	BCM58804,

	BCM58808,
@@ -1802,14 +1957,14 @@ struct bnxt { 
#define CHIP_NUM_57504		0x1751

#define CHIP_NUM_57502		0x1752



#define CHIP_NUM_57608		0x1760



#define CHIP_NUM_58802		0xd802

#define CHIP_NUM_58804		0xd804

#define CHIP_NUM_58808		0xd808



	u8			chip_rev;



#define CHIP_NUM_58818		0xd818



#define BNXT_CHIP_NUM_5730X(chip_num)		\

	((chip_num) >= CHIP_NUM_57301 &&	\

	 (chip_num) <= CHIP_NUM_57304)
@@ -1878,8 +2033,6 @@ struct bnxt { 
	#define BNXT_FLAG_RFS		0x100

	#define BNXT_FLAG_SHARED_RINGS	0x200

	#define BNXT_FLAG_PORT_STATS	0x400

	#define BNXT_FLAG_UDP_RSS_CAP	0x800

	#define BNXT_FLAG_NEW_RSS_CAP	0x2000

	#define BNXT_FLAG_WOL_CAP	0x4000

	#define BNXT_FLAG_ROCEV1_CAP	0x8000

	#define BNXT_FLAG_ROCEV2_CAP	0x10000
@@ -1887,7 +2040,7 @@ struct bnxt { 
					 BNXT_FLAG_ROCEV2_CAP)

	#define BNXT_FLAG_NO_AGG_RINGS	0x20000

	#define BNXT_FLAG_RX_PAGE_MODE	0x40000

	#define BNXT_FLAG_CHIP_SR2	0x80000

	#define BNXT_FLAG_CHIP_P7	0x80000

	#define BNXT_FLAG_MULTI_HOST	0x100000

	#define BNXT_FLAG_DSN_VALID	0x200000

	#define BNXT_FLAG_DOUBLE_DB	0x400000
@@ -1917,8 +2070,8 @@ struct bnxt { 
				  (bp)->max_tpa_v2) && !is_kdump_kernel())

#define BNXT_RX_JUMBO_MODE(bp)	((bp)->flags & BNXT_FLAG_JUMBO)



#define BNXT_CHIP_SR2(bp)			\

	((bp)->chip_num == CHIP_NUM_58818)

#define BNXT_CHIP_P7(bp)			\

	((bp)->chip_num == CHIP_NUM_57608)



#define BNXT_CHIP_P5(bp)			\

	((bp)->chip_num == CHIP_NUM_57508 ||	\
@@ -1927,7 +2080,7 @@ struct bnxt { 


/* Chip class phase 5 */

#define BNXT_CHIP_P5_PLUS(bp)			\

	(BNXT_CHIP_P5(bp) || BNXT_CHIP_SR2(bp))

	(BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))



/* Chip class phase 4.x */

#define BNXT_CHIP_P4(bp)			\
@@ -1999,6 +2152,11 @@ struct bnxt { 
	u16			rss_indir_tbl_entries;

	u32			rss_hash_cfg;

	u32			rss_hash_delta;

	u32			rss_cap;

#define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA	BIT(0)

#define BNXT_RSS_CAP_UDP_RSS_CAP		BIT(1)

#define BNXT_RSS_CAP_NEW_RSS_CAP		BIT(2)

#define BNXT_RSS_CAP_RSS_TCAM			BIT(3)



	u16			max_mtu;

	u8			max_tc;
@@ -2064,7 +2222,6 @@ struct bnxt { 
	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	BIT_ULL(16)

	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	BIT_ULL(17)

	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		BIT_ULL(18)

	#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA		BIT_ULL(19)

	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		BIT_ULL(20)

	#define BNXT_FW_CAP_HOT_RESET			BIT_ULL(21)

	#define BNXT_FW_CAP_PTP_RTC			BIT_ULL(22)
@@ -2195,6 +2352,7 @@ struct bnxt { 
	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */

	spinlock_t		db_lock;

#endif

	int			db_offset;	/* db_offset within db_size */

	int			db_size;



#define BNXT_NTP_FLTR_MAX_FLTR	4096
@@ -2228,6 +2386,7 @@ struct bnxt { 
#define BNXT_PHY_FL_NO_PAUSE		(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)

#define BNXT_PHY_FL_NO_PFC		(PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)

#define BNXT_PHY_FL_BANK_SEL		(PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)

#define BNXT_PHY_FL_SPEEDS2		(PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)



	u8			num_tests;

	struct bnxt_test_info	*test_info;
@@ -2271,15 +2430,15 @@ struct bnxt { 
#define BNXT_NUM_TX_RING_STATS			8

#define BNXT_NUM_TPA_RING_STATS			4

#define BNXT_NUM_TPA_RING_STATS_P5		5

#define BNXT_NUM_TPA_RING_STATS_P5_SR2		6

#define BNXT_NUM_TPA_RING_STATS_P7		6



#define BNXT_RING_STATS_SIZE_P5					\

	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\

	  BNXT_NUM_TPA_RING_STATS_P5) * 8)



#define BNXT_RING_STATS_SIZE_P5_SR2				\

#define BNXT_RING_STATS_SIZE_P7					\

	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\

	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)

	  BNXT_NUM_TPA_RING_STATS_P7) * 8)



#define BNXT_GET_RING_STATS64(sw, counter)		\

	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

+266 −49

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+387 −134

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c

+4 −6
Original line number Diff line number Diff line
@@ -42,15 +42,12 @@ static void bnxt_fill_msix_vecs(struct bnxt *bp, struct bnxt_msix_entry *ent) 
	for (i = 0; i < num_msix; i++) {

		ent[i].vector = bp->irq_tbl[idx + i].vector;

		ent[i].ring_idx = idx + i;

		if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {

			ent[i].db_offset = DB_PF_OFFSET_P5;

			if (BNXT_VF(bp))

				ent[i].db_offset = DB_VF_OFFSET_P5;

		} else {

		if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)

			ent[i].db_offset = bp->db_offset;

		else

			ent[i].db_offset = (idx + i) * 0x80;

	}

}

}



int bnxt_register_dev(struct bnxt_en_dev *edev,

		      struct bnxt_ulp_ops *ulp_ops,
@@ -333,6 +330,7 @@ static void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt *bp) 
	edev->pdev = bp->pdev;

	edev->l2_db_size = bp->db_size;

	edev->l2_db_size_nc = bp->db_size;

	edev->l2_db_offset = bp->db_offset;



	if (bp->flags & BNXT_FLAG_ROCEV1_CAP)

		edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP;