Commit 3743fda7 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'support-some-features-for-the-hns3-ethernet-driver' 

Jijie Shao says:

====================
Support some features for the HNS3 ethernet driver

Currently, the hns3 driver does not have the trace
of the command queue. As a result, it is difficult to
locate the communication between the driver and firmware.
Therefore, the trace function of the command queue is
added in this patch set to facilitate the locating of
communication problems between the driver and firmware.

If a RAS occurs, the driver will automatically reset to attempt
to recover the RAS. Therefore, to locate the cause of the RAS,
it is necessary to save the values of some RAS-related registers
before the reset. So we added a patch in this patch set to
print these information.
====================

Link: https://lore.kernel.org/r/20240410125354.2177067-1-shaojijie@huawei.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents a799de0e a1e5de0d

Documentation/networking/devlink/hns3.rst

+5 −0
Original line number Diff line number Diff line
@@ -23,3 +23,8 @@ The ``hns3`` driver reports the following versions 
   * - ``fw``

     - running

     - Used to represent the firmware version.

   * - ``fw.scc``

     - running

     - Used to represent the Soft Congestion Control (SSC) firmware version.

       SCC is a firmware component which provides multiple RDMA congestion

       control algorithms, including DCQCN.

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+13 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_WOL_B,

	HNAE3_DEV_SUPPORT_TM_FLUSH_B,

	HNAE3_DEV_SUPPORT_VF_FAULT_B,

	HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B,

};



#define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -181,6 +182,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_ae_dev_vf_fault_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)



#define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps)



enum HNAE3_PF_CAP_BITS {

	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,

};
@@ -362,6 +366,15 @@ struct hnae3_vector_info { 
#define HNAE3_FW_VERSION_BYTE0_SHIFT	0

#define HNAE3_FW_VERSION_BYTE0_MASK	GENMASK(7, 0)



#define HNAE3_SCC_VERSION_BYTE3_SHIFT	24

#define HNAE3_SCC_VERSION_BYTE3_MASK	GENMASK(31, 24)

#define HNAE3_SCC_VERSION_BYTE2_SHIFT	16

#define HNAE3_SCC_VERSION_BYTE2_MASK	GENMASK(23, 16)

#define HNAE3_SCC_VERSION_BYTE1_SHIFT	8

#define HNAE3_SCC_VERSION_BYTE1_MASK	GENMASK(15, 8)

#define HNAE3_SCC_VERSION_BYTE0_SHIFT	0

#define HNAE3_SCC_VERSION_BYTE0_MASK	GENMASK(7, 0)



struct hnae3_ring_chain_node {

	struct hnae3_ring_chain_node *next;

	u32 tqp_index;

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+19 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},

	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},

	{HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B},

	{HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B, HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
@@ -470,10 +471,14 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw, 
int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,

			int num)

{

	bool is_special = hclge_comm_is_special_opcode(le16_to_cpu(desc->opcode));

	struct hclge_comm_cmq_ring *csq = &hw->cmq.csq;

	int ret;

	int ntc;



	if (hw->cmq.ops.trace_cmd_send)

		hw->cmq.ops.trace_cmd_send(hw, desc, num, is_special);



	spin_lock_bh(&hw->cmq.csq.lock);



	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state)) {
@@ -507,6 +512,9 @@ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 


	spin_unlock_bh(&hw->cmq.csq.lock);



	if (hw->cmq.ops.trace_cmd_get)

		hw->cmq.ops.trace_cmd_get(hw, desc, num, is_special);



	return ret;

}
@@ -584,6 +592,17 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw) 
	return ret;

}



void hclge_comm_cmd_init_ops(struct hclge_comm_hw *hw,

			     const struct hclge_comm_cmq_ops *ops)

{

	struct hclge_comm_cmq *cmdq = &hw->cmq;



	if (ops) {

		cmdq->ops.trace_cmd_send = ops->trace_cmd_send;

		cmdq->ops.trace_cmd_get = ops->trace_cmd_get;

	}

}



int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,

			u32 *fw_version, bool is_pf,

			unsigned long reset_pending)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+23 −1
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ enum hclge_opcode_type { 
	HCLGE_OPC_DFX_RCB_REG		= 0x004D,

	HCLGE_OPC_DFX_TQP_REG		= 0x004E,

	HCLGE_OPC_DFX_SSU_REG_2		= 0x004F,

	HCLGE_OPC_DFX_GEN_REG		= 0x7038,



	HCLGE_OPC_QUERY_DEV_SPECS	= 0x0050,

	HCLGE_OPC_GET_QUEUE_ERR_VF      = 0x0067,
@@ -246,6 +247,9 @@ enum hclge_opcode_type { 
	HCLGE_OPC_QCN_AJUST_INIT	= 0x1A07,

	HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,



	/* SCC commands */

	HCLGE_OPC_QUERY_SCC_VER		= 0x1A84,



	/* Mailbox command */

	HCLGEVF_OPC_MBX_PF_TO_VF	= 0x2000,

	HCLGEVF_OPC_MBX_VF_TO_PF	= 0x2001,
@@ -353,6 +357,7 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_LANE_NUM_B = 27,

	HCLGE_COMM_CAP_WOL_B = 28,

	HCLGE_COMM_CAP_TM_FLUSH_B = 31,

	HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B = 32,

};



enum HCLGE_COMM_API_CAP_BITS {
@@ -392,6 +397,11 @@ struct hclge_comm_query_version_cmd { 
	__le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */

};



struct hclge_comm_query_scc_cmd {

	__le32 scc_version;

	u8 rsv[20];

};



#define HCLGE_DESC_DATA_LEN		6

struct hclge_desc {

	__le16 opcode;
@@ -423,11 +433,22 @@ enum hclge_comm_cmd_status { 
	HCLGE_COMM_ERR_CSQ_ERROR	= -3,

};



struct hclge_comm_hw;

struct hclge_comm_cmq_ops {

	void (*trace_cmd_send)(struct hclge_comm_hw *hw,

			       struct hclge_desc *desc,

			       int num, bool is_special);

	void (*trace_cmd_get)(struct hclge_comm_hw *hw,

			      struct hclge_desc *desc,

			      int num, bool is_special);

};



struct hclge_comm_cmq {

	struct hclge_comm_cmq_ring csq;

	struct hclge_comm_cmq_ring crq;

	u16 tx_timeout;

	enum hclge_comm_cmd_status last_status;

	struct hclge_comm_cmq_ops ops;

};



struct hclge_comm_hw {
@@ -474,5 +495,6 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw); 
int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,

			u32 *fw_version, bool is_pf,

			unsigned long reset_pending);



void hclge_comm_cmd_init_ops(struct hclge_comm_hw *hw,

			     const struct hclge_comm_cmq_ops *ops);

#endif

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

+642 −4
Original line number Diff line number Diff line
@@ -18,6 +18,646 @@ static const char * const hclge_mac_state_str[] = { 


static const char * const tc_map_mode_str[] = { "PRIO", "DSCP" };



static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {

	{false, "Reserved"},

	{true,	"BP_CPU_STATE"},

	{true,	"DFX_MSIX_INFO_NIC_0"},

	{true,	"DFX_MSIX_INFO_NIC_1"},

	{true,	"DFX_MSIX_INFO_NIC_2"},

	{true,	"DFX_MSIX_INFO_NIC_3"},



	{true,	"DFX_MSIX_INFO_ROC_0"},

	{true,	"DFX_MSIX_INFO_ROC_1"},

	{true,	"DFX_MSIX_INFO_ROC_2"},

	{true,	"DFX_MSIX_INFO_ROC_3"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = {

	{false, "Reserved"},

	{true,	"SSU_ETS_PORT_STATUS"},

	{true,	"SSU_ETS_TCG_STATUS"},

	{false, "Reserved"},

	{false, "Reserved"},

	{true,	"SSU_BP_STATUS_0"},



	{true,	"SSU_BP_STATUS_1"},

	{true,	"SSU_BP_STATUS_2"},

	{true,	"SSU_BP_STATUS_3"},

	{true,	"SSU_BP_STATUS_4"},

	{true,	"SSU_BP_STATUS_5"},

	{true,	"SSU_MAC_TX_PFC_IND"},



	{true,	"MAC_SSU_RX_PFC_IND"},

	{true,	"BTMP_AGEING_ST_B0"},

	{true,	"BTMP_AGEING_ST_B1"},

	{true,	"BTMP_AGEING_ST_B2"},

	{false, "Reserved"},

	{false, "Reserved"},



	{true,	"FULL_DROP_NUM"},

	{true,	"PART_DROP_NUM"},

	{true,	"PPP_KEY_DROP_NUM"},

	{true,	"PPP_RLT_DROP_NUM"},

	{true,	"LO_PRI_UNICAST_RLT_DROP_NUM"},

	{true,	"HI_PRI_MULTICAST_RLT_DROP_NUM"},



	{true,	"LO_PRI_MULTICAST_RLT_DROP_NUM"},

	{true,	"NCSI_PACKET_CURR_BUFFER_CNT"},

	{true,	"BTMP_AGEING_RLS_CNT_BANK0"},

	{true,	"BTMP_AGEING_RLS_CNT_BANK1"},

	{true,	"BTMP_AGEING_RLS_CNT_BANK2"},

	{true,	"SSU_MB_RD_RLT_DROP_CNT"},



	{true,	"SSU_PPP_MAC_KEY_NUM_L"},

	{true,	"SSU_PPP_MAC_KEY_NUM_H"},

	{true,	"SSU_PPP_HOST_KEY_NUM_L"},

	{true,	"SSU_PPP_HOST_KEY_NUM_H"},

	{true,	"PPP_SSU_MAC_RLT_NUM_L"},

	{true,	"PPP_SSU_MAC_RLT_NUM_H"},



	{true,	"PPP_SSU_HOST_RLT_NUM_L"},

	{true,	"PPP_SSU_HOST_RLT_NUM_H"},

	{true,	"NCSI_RX_PACKET_IN_CNT_L"},

	{true,	"NCSI_RX_PACKET_IN_CNT_H"},

	{true,	"NCSI_TX_PACKET_OUT_CNT_L"},

	{true,	"NCSI_TX_PACKET_OUT_CNT_H"},



	{true,	"SSU_KEY_DROP_NUM"},

	{true,	"MB_UNCOPY_NUM"},

	{true,	"RX_OQ_DROP_PKT_CNT"},

	{true,	"TX_OQ_DROP_PKT_CNT"},

	{true,	"BANK_UNBALANCE_DROP_CNT"},

	{true,	"BANK_UNBALANCE_RX_DROP_CNT"},



	{true,	"NIC_L2_ERR_DROP_PKT_CNT"},

	{true,	"ROC_L2_ERR_DROP_PKT_CNT"},

	{true,	"NIC_L2_ERR_DROP_PKT_CNT_RX"},

	{true,	"ROC_L2_ERR_DROP_PKT_CNT_RX"},

	{true,	"RX_OQ_GLB_DROP_PKT_CNT"},

	{false, "Reserved"},



	{true,	"LO_PRI_UNICAST_CUR_CNT"},

	{true,	"HI_PRI_MULTICAST_CUR_CNT"},

	{true,	"LO_PRI_MULTICAST_CUR_CNT"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = {

	{true,	"prt_id"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_0"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_1"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_2"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_3"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_4"},



	{true,	"PACKET_TC_CURR_BUFFER_CNT_5"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_6"},

	{true,	"PACKET_TC_CURR_BUFFER_CNT_7"},

	{true,	"PACKET_CURR_BUFFER_CNT"},

	{false, "Reserved"},

	{false, "Reserved"},



	{true,	"RX_PACKET_IN_CNT_L"},

	{true,	"RX_PACKET_IN_CNT_H"},

	{true,	"RX_PACKET_OUT_CNT_L"},

	{true,	"RX_PACKET_OUT_CNT_H"},

	{true,	"TX_PACKET_IN_CNT_L"},

	{true,	"TX_PACKET_IN_CNT_H"},



	{true,	"TX_PACKET_OUT_CNT_L"},

	{true,	"TX_PACKET_OUT_CNT_H"},

	{true,	"ROC_RX_PACKET_IN_CNT_L"},

	{true,	"ROC_RX_PACKET_IN_CNT_H"},

	{true,	"ROC_TX_PACKET_OUT_CNT_L"},

	{true,	"ROC_TX_PACKET_OUT_CNT_H"},



	{true,	"RX_PACKET_TC_IN_CNT_0_L"},

	{true,	"RX_PACKET_TC_IN_CNT_0_H"},

	{true,	"RX_PACKET_TC_IN_CNT_1_L"},

	{true,	"RX_PACKET_TC_IN_CNT_1_H"},

	{true,	"RX_PACKET_TC_IN_CNT_2_L"},

	{true,	"RX_PACKET_TC_IN_CNT_2_H"},



	{true,	"RX_PACKET_TC_IN_CNT_3_L"},

	{true,	"RX_PACKET_TC_IN_CNT_3_H"},

	{true,	"RX_PACKET_TC_IN_CNT_4_L"},

	{true,	"RX_PACKET_TC_IN_CNT_4_H"},

	{true,	"RX_PACKET_TC_IN_CNT_5_L"},

	{true,	"RX_PACKET_TC_IN_CNT_5_H"},



	{true,	"RX_PACKET_TC_IN_CNT_6_L"},

	{true,	"RX_PACKET_TC_IN_CNT_6_H"},

	{true,	"RX_PACKET_TC_IN_CNT_7_L"},

	{true,	"RX_PACKET_TC_IN_CNT_7_H"},

	{true,	"RX_PACKET_TC_OUT_CNT_0_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_0_H"},



	{true,	"RX_PACKET_TC_OUT_CNT_1_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_1_H"},

	{true,	"RX_PACKET_TC_OUT_CNT_2_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_2_H"},

	{true,	"RX_PACKET_TC_OUT_CNT_3_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_3_H"},



	{true,	"RX_PACKET_TC_OUT_CNT_4_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_4_H"},

	{true,	"RX_PACKET_TC_OUT_CNT_5_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_5_H"},

	{true,	"RX_PACKET_TC_OUT_CNT_6_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_6_H"},



	{true,	"RX_PACKET_TC_OUT_CNT_7_L"},

	{true,	"RX_PACKET_TC_OUT_CNT_7_H"},

	{true,	"TX_PACKET_TC_IN_CNT_0_L"},

	{true,	"TX_PACKET_TC_IN_CNT_0_H"},

	{true,	"TX_PACKET_TC_IN_CNT_1_L"},

	{true,	"TX_PACKET_TC_IN_CNT_1_H"},



	{true,	"TX_PACKET_TC_IN_CNT_2_L"},

	{true,	"TX_PACKET_TC_IN_CNT_2_H"},

	{true,	"TX_PACKET_TC_IN_CNT_3_L"},

	{true,	"TX_PACKET_TC_IN_CNT_3_H"},

	{true,	"TX_PACKET_TC_IN_CNT_4_L"},

	{true,	"TX_PACKET_TC_IN_CNT_4_H"},



	{true,	"TX_PACKET_TC_IN_CNT_5_L"},

	{true,	"TX_PACKET_TC_IN_CNT_5_H"},

	{true,	"TX_PACKET_TC_IN_CNT_6_L"},

	{true,	"TX_PACKET_TC_IN_CNT_6_H"},

	{true,	"TX_PACKET_TC_IN_CNT_7_L"},

	{true,	"TX_PACKET_TC_IN_CNT_7_H"},



	{true,	"TX_PACKET_TC_OUT_CNT_0_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_0_H"},

	{true,	"TX_PACKET_TC_OUT_CNT_1_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_1_H"},

	{true,	"TX_PACKET_TC_OUT_CNT_2_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_2_H"},



	{true,	"TX_PACKET_TC_OUT_CNT_3_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_3_H"},

	{true,	"TX_PACKET_TC_OUT_CNT_4_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_4_H"},

	{true,	"TX_PACKET_TC_OUT_CNT_5_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_5_H"},



	{true,	"TX_PACKET_TC_OUT_CNT_6_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_6_H"},

	{true,	"TX_PACKET_TC_OUT_CNT_7_L"},

	{true,	"TX_PACKET_TC_OUT_CNT_7_H"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = {

	{true,	"OQ_INDEX"},

	{true,	"QUEUE_CNT"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = {

	{true,	"prt_id"},

	{true,	"IGU_RX_ERR_PKT"},

	{true,	"IGU_RX_NO_SOF_PKT"},

	{true,	"EGU_TX_1588_SHORT_PKT"},

	{true,	"EGU_TX_1588_PKT"},

	{true,	"EGU_TX_ERR_PKT"},



	{true,	"IGU_RX_OUT_L2_PKT"},

	{true,	"IGU_RX_OUT_L3_PKT"},

	{true,	"IGU_RX_OUT_L4_PKT"},

	{true,	"IGU_RX_IN_L2_PKT"},

	{true,	"IGU_RX_IN_L3_PKT"},

	{true,	"IGU_RX_IN_L4_PKT"},



	{true,	"IGU_RX_EL3E_PKT"},

	{true,	"IGU_RX_EL4E_PKT"},

	{true,	"IGU_RX_L3E_PKT"},

	{true,	"IGU_RX_L4E_PKT"},

	{true,	"IGU_RX_ROCEE_PKT"},

	{true,	"IGU_RX_OUT_UDP0_PKT"},



	{true,	"IGU_RX_IN_UDP0_PKT"},

	{true,	"IGU_MC_CAR_DROP_PKT_L"},

	{true,	"IGU_MC_CAR_DROP_PKT_H"},

	{true,	"IGU_BC_CAR_DROP_PKT_L"},

	{true,	"IGU_BC_CAR_DROP_PKT_H"},

	{false, "Reserved"},



	{true,	"IGU_RX_OVERSIZE_PKT_L"},

	{true,	"IGU_RX_OVERSIZE_PKT_H"},

	{true,	"IGU_RX_UNDERSIZE_PKT_L"},

	{true,	"IGU_RX_UNDERSIZE_PKT_H"},

	{true,	"IGU_RX_OUT_ALL_PKT_L"},

	{true,	"IGU_RX_OUT_ALL_PKT_H"},



	{true,	"IGU_TX_OUT_ALL_PKT_L"},

	{true,	"IGU_TX_OUT_ALL_PKT_H"},

	{true,	"IGU_RX_UNI_PKT_L"},

	{true,	"IGU_RX_UNI_PKT_H"},

	{true,	"IGU_RX_MULTI_PKT_L"},

	{true,	"IGU_RX_MULTI_PKT_H"},



	{true,	"IGU_RX_BROAD_PKT_L"},

	{true,	"IGU_RX_BROAD_PKT_H"},

	{true,	"EGU_TX_OUT_ALL_PKT_L"},

	{true,	"EGU_TX_OUT_ALL_PKT_H"},

	{true,	"EGU_TX_UNI_PKT_L"},

	{true,	"EGU_TX_UNI_PKT_H"},



	{true,	"EGU_TX_MULTI_PKT_L"},

	{true,	"EGU_TX_MULTI_PKT_H"},

	{true,	"EGU_TX_BROAD_PKT_L"},

	{true,	"EGU_TX_BROAD_PKT_H"},

	{true,	"IGU_TX_KEY_NUM_L"},

	{true,	"IGU_TX_KEY_NUM_H"},



	{true,	"IGU_RX_NON_TUN_PKT_L"},

	{true,	"IGU_RX_NON_TUN_PKT_H"},

	{true,	"IGU_RX_TUN_PKT_L"},

	{true,	"IGU_RX_TUN_PKT_H"},

	{false,	"Reserved"},

	{false,	"Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = {

	{true, "tc_queue_num"},

	{true, "FSM_DFX_ST0"},

	{true, "FSM_DFX_ST1"},

	{true, "RPU_RX_PKT_DROP_CNT"},

	{true, "BUF_WAIT_TIMEOUT"},

	{true, "BUF_WAIT_TIMEOUT_QID"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = {

	{false, "Reserved"},

	{true,	"FIFO_DFX_ST0"},

	{true,	"FIFO_DFX_ST1"},

	{true,	"FIFO_DFX_ST2"},

	{true,	"FIFO_DFX_ST3"},

	{true,	"FIFO_DFX_ST4"},



	{true,	"FIFO_DFX_ST5"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = {

	{false, "Reserved"},

	{true,	"NCSI_EGU_TX_FIFO_STS"},

	{true,	"NCSI_PAUSE_STATUS"},

	{true,	"NCSI_RX_CTRL_DMAC_ERR_CNT"},

	{true,	"NCSI_RX_CTRL_SMAC_ERR_CNT"},

	{true,	"NCSI_RX_CTRL_CKS_ERR_CNT"},



	{true,	"NCSI_RX_CTRL_PKT_CNT"},

	{true,	"NCSI_RX_PT_DMAC_ERR_CNT"},

	{true,	"NCSI_RX_PT_SMAC_ERR_CNT"},

	{true,	"NCSI_RX_PT_PKT_CNT"},

	{true,	"NCSI_RX_FCS_ERR_CNT"},

	{true,	"NCSI_TX_CTRL_DMAC_ERR_CNT"},



	{true,	"NCSI_TX_CTRL_SMAC_ERR_CNT"},

	{true,	"NCSI_TX_CTRL_PKT_CNT"},

	{true,	"NCSI_TX_PT_DMAC_ERR_CNT"},

	{true,	"NCSI_TX_PT_SMAC_ERR_CNT"},

	{true,	"NCSI_TX_PT_PKT_CNT"},

	{true,	"NCSI_TX_PT_PKT_TRUNC_CNT"},



	{true,	"NCSI_TX_PT_PKT_ERR_CNT"},

	{true,	"NCSI_TX_CTRL_PKT_ERR_CNT"},

	{true,	"NCSI_RX_CTRL_PKT_TRUNC_CNT"},

	{true,	"NCSI_RX_CTRL_PKT_CFLIT_CNT"},

	{false, "Reserved"},

	{false, "Reserved"},



	{true,	"NCSI_MAC_RX_OCTETS_OK"},

	{true,	"NCSI_MAC_RX_OCTETS_BAD"},

	{true,	"NCSI_MAC_RX_UC_PKTS"},

	{true,	"NCSI_MAC_RX_MC_PKTS"},

	{true,	"NCSI_MAC_RX_BC_PKTS"},

	{true,	"NCSI_MAC_RX_PKTS_64OCTETS"},



	{true,	"NCSI_MAC_RX_PKTS_65TO127OCTETS"},

	{true,	"NCSI_MAC_RX_PKTS_128TO255OCTETS"},

	{true,	"NCSI_MAC_RX_PKTS_255TO511OCTETS"},

	{true,	"NCSI_MAC_RX_PKTS_512TO1023OCTETS"},

	{true,	"NCSI_MAC_RX_PKTS_1024TO1518OCTETS"},

	{true,	"NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"},



	{true,	"NCSI_MAC_RX_FCS_ERRORS"},

	{true,	"NCSI_MAC_RX_LONG_ERRORS"},

	{true,	"NCSI_MAC_RX_JABBER_ERRORS"},

	{true,	"NCSI_MAC_RX_RUNT_ERR_CNT"},

	{true,	"NCSI_MAC_RX_SHORT_ERR_CNT"},

	{true,	"NCSI_MAC_RX_FILT_PKT_CNT"},



	{true,	"NCSI_MAC_RX_OCTETS_TOTAL_FILT"},

	{true,	"NCSI_MAC_TX_OCTETS_OK"},

	{true,	"NCSI_MAC_TX_OCTETS_BAD"},

	{true,	"NCSI_MAC_TX_UC_PKTS"},

	{true,	"NCSI_MAC_TX_MC_PKTS"},

	{true,	"NCSI_MAC_TX_BC_PKTS"},



	{true,	"NCSI_MAC_TX_PKTS_64OCTETS"},

	{true,	"NCSI_MAC_TX_PKTS_65TO127OCTETS"},

	{true,	"NCSI_MAC_TX_PKTS_128TO255OCTETS"},

	{true,	"NCSI_MAC_TX_PKTS_256TO511OCTETS"},

	{true,	"NCSI_MAC_TX_PKTS_512TO1023OCTETS"},

	{true,	"NCSI_MAC_TX_PKTS_1024TO1518OCTETS"},



	{true,	"NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"},

	{true,	"NCSI_MAC_TX_UNDERRUN"},

	{true,	"NCSI_MAC_TX_CRC_ERROR"},

	{true,	"NCSI_MAC_TX_PAUSE_FRAMES"},

	{true,	"NCSI_MAC_RX_PAD_PKTS"},

	{true,	"NCSI_MAC_RX_PAUSE_FRAMES"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = {

	{false, "Reserved"},

	{true,	"LGE_IGU_AFIFO_DFX_0"},

	{true,	"LGE_IGU_AFIFO_DFX_1"},

	{true,	"LGE_IGU_AFIFO_DFX_2"},

	{true,	"LGE_IGU_AFIFO_DFX_3"},

	{true,	"LGE_IGU_AFIFO_DFX_4"},



	{true,	"LGE_IGU_AFIFO_DFX_5"},

	{true,	"LGE_IGU_AFIFO_DFX_6"},

	{true,	"LGE_IGU_AFIFO_DFX_7"},

	{true,	"LGE_EGU_AFIFO_DFX_0"},

	{true,	"LGE_EGU_AFIFO_DFX_1"},

	{true,	"LGE_EGU_AFIFO_DFX_2"},



	{true,	"LGE_EGU_AFIFO_DFX_3"},

	{true,	"LGE_EGU_AFIFO_DFX_4"},

	{true,	"LGE_EGU_AFIFO_DFX_5"},

	{true,	"LGE_EGU_AFIFO_DFX_6"},

	{true,	"LGE_EGU_AFIFO_DFX_7"},

	{true,	"CGE_IGU_AFIFO_DFX_0"},



	{true,	"CGE_IGU_AFIFO_DFX_1"},

	{true,	"CGE_EGU_AFIFO_DFX_0"},

	{true,	"CGE_EGU_AFIFO_DFX_1"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = {

	{false, "Reserved"},

	{true,	"DROP_FROM_PRT_PKT_CNT"},

	{true,	"DROP_FROM_HOST_PKT_CNT"},

	{true,	"DROP_TX_VLAN_PROC_CNT"},

	{true,	"DROP_MNG_CNT"},

	{true,	"DROP_FD_CNT"},



	{true,	"DROP_NO_DST_CNT"},

	{true,	"DROP_MC_MBID_FULL_CNT"},

	{true,	"DROP_SC_FILTERED"},

	{true,	"PPP_MC_DROP_PKT_CNT"},

	{true,	"DROP_PT_CNT"},

	{true,	"DROP_MAC_ANTI_SPOOF_CNT"},



	{true,	"DROP_IG_VFV_CNT"},

	{true,	"DROP_IG_PRTV_CNT"},

	{true,	"DROP_CNM_PFC_PAUSE_CNT"},

	{true,	"DROP_TORUS_TC_CNT"},

	{true,	"DROP_TORUS_LPBK_CNT"},

	{true,	"PPP_HFS_STS"},



	{true,	"PPP_MC_RSLT_STS"},

	{true,	"PPP_P3U_STS"},

	{true,	"PPP_RSLT_DESCR_STS"},

	{true,	"PPP_UMV_STS_0"},

	{true,	"PPP_UMV_STS_1"},

	{true,	"PPP_VFV_STS"},



	{true,	"PPP_GRO_KEY_CNT"},

	{true,	"PPP_GRO_INFO_CNT"},

	{true,	"PPP_GRO_DROP_CNT"},

	{true,	"PPP_GRO_OUT_CNT"},

	{true,	"PPP_GRO_KEY_MATCH_DATA_CNT"},

	{true,	"PPP_GRO_KEY_MATCH_TCAM_CNT"},



	{true,	"PPP_GRO_INFO_MATCH_CNT"},

	{true,	"PPP_GRO_FREE_ENTRY_CNT"},

	{true,	"PPP_GRO_INNER_DFX_SIGNAL"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},



	{true,	"GET_RX_PKT_CNT_L"},

	{true,	"GET_RX_PKT_CNT_H"},

	{true,	"GET_TX_PKT_CNT_L"},

	{true,	"GET_TX_PKT_CNT_H"},

	{true,	"SEND_UC_PRT2HOST_PKT_CNT_L"},

	{true,	"SEND_UC_PRT2HOST_PKT_CNT_H"},



	{true,	"SEND_UC_PRT2PRT_PKT_CNT_L"},

	{true,	"SEND_UC_PRT2PRT_PKT_CNT_H"},

	{true,	"SEND_UC_HOST2HOST_PKT_CNT_L"},

	{true,	"SEND_UC_HOST2HOST_PKT_CNT_H"},

	{true,	"SEND_UC_HOST2PRT_PKT_CNT_L"},

	{true,	"SEND_UC_HOST2PRT_PKT_CNT_H"},



	{true,	"SEND_MC_FROM_PRT_CNT_L"},

	{true,	"SEND_MC_FROM_PRT_CNT_H"},

	{true,	"SEND_MC_FROM_HOST_CNT_L"},

	{true,	"SEND_MC_FROM_HOST_CNT_H"},

	{true,	"SSU_MC_RD_CNT_L"},

	{true,	"SSU_MC_RD_CNT_H"},



	{true,	"SSU_MC_DROP_CNT_L"},

	{true,	"SSU_MC_DROP_CNT_H"},

	{true,	"SSU_MC_RD_PKT_CNT_L"},

	{true,	"SSU_MC_RD_PKT_CNT_H"},

	{true,	"PPP_MC_2HOST_PKT_CNT_L"},

	{true,	"PPP_MC_2HOST_PKT_CNT_H"},



	{true,	"PPP_MC_2PRT_PKT_CNT_L"},

	{true,	"PPP_MC_2PRT_PKT_CNT_H"},

	{true,	"NTSNOS_PKT_CNT_L"},

	{true,	"NTSNOS_PKT_CNT_H"},

	{true,	"NTUP_PKT_CNT_L"},

	{true,	"NTUP_PKT_CNT_H"},



	{true,	"NTLCL_PKT_CNT_L"},

	{true,	"NTLCL_PKT_CNT_H"},

	{true,	"NTTGT_PKT_CNT_L"},

	{true,	"NTTGT_PKT_CNT_H"},

	{true,	"RTNS_PKT_CNT_L"},

	{true,	"RTNS_PKT_CNT_H"},



	{true,	"RTLPBK_PKT_CNT_L"},

	{true,	"RTLPBK_PKT_CNT_H"},

	{true,	"NR_PKT_CNT_L"},

	{true,	"NR_PKT_CNT_H"},

	{true,	"RR_PKT_CNT_L"},

	{true,	"RR_PKT_CNT_H"},



	{true,	"MNG_TBL_HIT_CNT_L"},

	{true,	"MNG_TBL_HIT_CNT_H"},

	{true,	"FD_TBL_HIT_CNT_L"},

	{true,	"FD_TBL_HIT_CNT_H"},

	{true,	"FD_LKUP_CNT_L"},

	{true,	"FD_LKUP_CNT_H"},



	{true,	"BC_HIT_CNT_L"},

	{true,	"BC_HIT_CNT_H"},

	{true,	"UM_TBL_UC_HIT_CNT_L"},

	{true,	"UM_TBL_UC_HIT_CNT_H"},

	{true,	"UM_TBL_MC_HIT_CNT_L"},

	{true,	"UM_TBL_MC_HIT_CNT_H"},



	{true,	"UM_TBL_VMDQ1_HIT_CNT_L"},

	{true,	"UM_TBL_VMDQ1_HIT_CNT_H"},

	{true,	"MTA_TBL_HIT_CNT_L"},

	{true,	"MTA_TBL_HIT_CNT_H"},

	{true,	"FWD_BONDING_HIT_CNT_L"},

	{true,	"FWD_BONDING_HIT_CNT_H"},



	{true,	"PROMIS_TBL_HIT_CNT_L"},

	{true,	"PROMIS_TBL_HIT_CNT_H"},

	{true,	"GET_TUNL_PKT_CNT_L"},

	{true,	"GET_TUNL_PKT_CNT_H"},

	{true,	"GET_BMC_PKT_CNT_L"},

	{true,	"GET_BMC_PKT_CNT_H"},



	{true,	"SEND_UC_PRT2BMC_PKT_CNT_L"},

	{true,	"SEND_UC_PRT2BMC_PKT_CNT_H"},

	{true,	"SEND_UC_HOST2BMC_PKT_CNT_L"},

	{true,	"SEND_UC_HOST2BMC_PKT_CNT_H"},

	{true,	"SEND_UC_BMC2HOST_PKT_CNT_L"},

	{true,	"SEND_UC_BMC2HOST_PKT_CNT_H"},



	{true,	"SEND_UC_BMC2PRT_PKT_CNT_L"},

	{true,	"SEND_UC_BMC2PRT_PKT_CNT_H"},

	{true,	"PPP_MC_2BMC_PKT_CNT_L"},

	{true,	"PPP_MC_2BMC_PKT_CNT_H"},

	{true,	"VLAN_MIRR_CNT_L"},

	{true,	"VLAN_MIRR_CNT_H"},



	{true,	"IG_MIRR_CNT_L"},

	{true,	"IG_MIRR_CNT_H"},

	{true,	"EG_MIRR_CNT_L"},

	{true,	"EG_MIRR_CNT_H"},

	{true,	"RX_DEFAULT_HOST_HIT_CNT_L"},

	{true,	"RX_DEFAULT_HOST_HIT_CNT_H"},



	{true,	"LAN_PAIR_CNT_L"},

	{true,	"LAN_PAIR_CNT_H"},

	{true,	"UM_TBL_MC_HIT_PKT_CNT_L"},

	{true,	"UM_TBL_MC_HIT_PKT_CNT_H"},

	{true,	"MTA_TBL_HIT_PKT_CNT_L"},

	{true,	"MTA_TBL_HIT_PKT_CNT_H"},



	{true,	"PROMIS_TBL_HIT_PKT_CNT_L"},

	{true,	"PROMIS_TBL_HIT_PKT_CNT_H"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = {

	{false, "Reserved"},

	{true,	"FSM_DFX_ST0"},

	{true,	"FSM_DFX_ST1"},

	{true,	"FSM_DFX_ST2"},

	{true,	"FIFO_DFX_ST0"},

	{true,	"FIFO_DFX_ST1"},



	{true,	"FIFO_DFX_ST2"},

	{true,	"FIFO_DFX_ST3"},

	{true,	"FIFO_DFX_ST4"},

	{true,	"FIFO_DFX_ST5"},

	{true,	"FIFO_DFX_ST6"},

	{true,	"FIFO_DFX_ST7"},



	{true,	"FIFO_DFX_ST8"},

	{true,	"FIFO_DFX_ST9"},

	{true,	"FIFO_DFX_ST10"},

	{true,	"FIFO_DFX_ST11"},

	{true,	"Q_CREDIT_VLD_0"},

	{true,	"Q_CREDIT_VLD_1"},



	{true,	"Q_CREDIT_VLD_2"},

	{true,	"Q_CREDIT_VLD_3"},

	{true,	"Q_CREDIT_VLD_4"},

	{true,	"Q_CREDIT_VLD_5"},

	{true,	"Q_CREDIT_VLD_6"},

	{true,	"Q_CREDIT_VLD_7"},



	{true,	"Q_CREDIT_VLD_8"},

	{true,	"Q_CREDIT_VLD_9"},

	{true,	"Q_CREDIT_VLD_10"},

	{true,	"Q_CREDIT_VLD_11"},

	{true,	"Q_CREDIT_VLD_12"},

	{true,	"Q_CREDIT_VLD_13"},



	{true,	"Q_CREDIT_VLD_14"},

	{true,	"Q_CREDIT_VLD_15"},

	{true,	"Q_CREDIT_VLD_16"},

	{true,	"Q_CREDIT_VLD_17"},

	{true,	"Q_CREDIT_VLD_18"},

	{true,	"Q_CREDIT_VLD_19"},



	{true,	"Q_CREDIT_VLD_20"},

	{true,	"Q_CREDIT_VLD_21"},

	{true,	"Q_CREDIT_VLD_22"},

	{true,	"Q_CREDIT_VLD_23"},

	{true,	"Q_CREDIT_VLD_24"},

	{true,	"Q_CREDIT_VLD_25"},



	{true,	"Q_CREDIT_VLD_26"},

	{true,	"Q_CREDIT_VLD_27"},

	{true,	"Q_CREDIT_VLD_28"},

	{true,	"Q_CREDIT_VLD_29"},

	{true,	"Q_CREDIT_VLD_30"},

	{true,	"Q_CREDIT_VLD_31"},



	{true,	"GRO_BD_SERR_CNT"},

	{true,	"GRO_CONTEXT_SERR_CNT"},

	{true,	"RX_STASH_CFG_SERR_CNT"},

	{true,	"AXI_RD_FBD_SERR_CNT"},

	{true,	"GRO_BD_MERR_CNT"},

	{true,	"GRO_CONTEXT_MERR_CNT"},



	{true,	"RX_STASH_CFG_MERR_CNT"},

	{true,	"AXI_RD_FBD_MERR_CNT"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

	{false, "Reserved"},

};



static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = {

	{true, "q_num"},

	{true, "RCB_CFG_RX_RING_TAIL"},

	{true, "RCB_CFG_RX_RING_HEAD"},

	{true, "RCB_CFG_RX_RING_FBDNUM"},

	{true, "RCB_CFG_RX_RING_OFFSET"},

	{true, "RCB_CFG_RX_RING_FBDOFFSET"},



	{true, "RCB_CFG_RX_RING_PKTNUM_RECORD"},

	{true, "RCB_CFG_TX_RING_TAIL"},

	{true, "RCB_CFG_TX_RING_HEAD"},

	{true, "RCB_CFG_TX_RING_FBDNUM"},

	{true, "RCB_CFG_TX_RING_OFFSET"},

	{true, "RCB_CFG_TX_RING_EBDNUM"},

};



static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = {

	{ .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,

	  .dfx_msg = &hclge_dbg_bios_common_reg[0],
@@ -161,10 +801,8 @@ static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset, 
	return 0;

}



static int hclge_dbg_cmd_send(struct hclge_dev *hdev,

			      struct hclge_desc *desc_src,

			      int index, int bd_num,

			      enum hclge_opcode_type cmd)

int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src,

		       int index, int bd_num, enum hclge_opcode_type cmd)

{

	struct hclge_desc *desc = desc_src;

	int ret, i;