Commit 375ee44a authored by Adam Ford's avatar Adam Ford Committed by Vinod Koul
Browse files

phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup 



The value of 'S' is writen to two places, PHY_REG3[7:4] and
PHY_REG21[3:0].  There is a lookup table which contains
the value of PHY_REG3.  Rather than using a switch statement
based on the pixel clock to search for the value of 'S' again,
just shift the contents of PHY_REG3[7:4] >> 4 and place the value
in PHY_REG21[3:0].  Doing this can eliminate an entire function.

Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Reviewed-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Reviewed-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: default avatarDominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: default avatarDominique Martinet <dominique.martinet@atmark-techno.com>
Link: https://lore.kernel.org/r/20240914112816.520224-3-aford173@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 4a5a9e25

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

+4 −35
Original line number Diff line number Diff line
@@ -364,40 +364,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) 
	return container_of(hw, struct fsl_samsung_hdmi_phy, hw);

}



static void

fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy,

				      const struct phy_config *cfg)

{

	u8 div = 0x1;



	switch (cfg->pixclk) {

	case  22250000 ...  33750000:

		div = 0xf;

		break;

	case  35000000 ...  40000000:

		div = 0xb;

		break;

	case  43200000 ...  47500000:

		div = 0x9;

		break;

	case  50349650 ...  63500000:

		div = 0x7;

		break;

	case  67500000 ...  90000000:

		div = 0x5;

		break;

	case  94000000 ... 148500000:

		div = 0x3;

		break;

	case 154000000 ... 297000000:

		div = 0x1;

		break;

	}



	writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div),

	       phy->regs + PHY_REG(21));

}



static void

fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,

					    const struct phy_config *cfg)
@@ -466,7 +432,10 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, 
	for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)

		writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4);



	fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg);

	/* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */

	writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK,

	       cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21));



	fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);



	writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));