Commit 3767def1 authored by Babu Moger's avatar Babu Moger Committed by Borislav Petkov (AMD)
Browse files

x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement 

Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion
of data from I/O devices into the L3 cache. By directly caching data from I/O
devices rather than first storing the I/O data in DRAM, SDCI reduces demands on
DRAM bandwidth and reduces latency to the processor consuming the I/O data.

The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to
control the portion of the L3 cache used for SDCI.

When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache
partitions identified by the highest-supported L3_MASK_n register, where n is
the maximum supported CLOSID.

Add CPUID feature bit that can be used to configure SDCIAE.

The SDCIAE feature details are documented in:

  AMD64 Architecture Programmer's Manual Volume 2: System Programming
     Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
    Injection Allocation Enforcement (SDCIAE).

available at https://bugzilla.kernel.org/show_bug.cgi?id=206537



Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Acked-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/83ca10d981c48e86df2c3ad9658bb3ba3544c763.1762995456.git.babu.moger@amd.com
parent 5a88a6e9

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -500,6 +500,8 @@ 
#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */

#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */



#define X86_FEATURE_SDCIAE		(21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */



/*

 * BUG word(s)

 */

arch/x86/kernel/cpu/cpuid-deps.c

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ static const struct cpuid_dep cpuid_deps[] = { 
	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },

	{ X86_FEATURE_BMEC,			X86_FEATURE_CQM_MBM_TOTAL   },

	{ X86_FEATURE_BMEC,			X86_FEATURE_CQM_MBM_LOCAL   },

	{ X86_FEATURE_SDCIAE,			X86_FEATURE_CAT_L3    },

	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },

	{ X86_FEATURE_AVX512_FP16,		X86_FEATURE_AVX512BW  },

	{ X86_FEATURE_ENQCMD,			X86_FEATURE_XSAVES    },

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_SMBA,			CPUID_EBX,  2, 0x80000020, 0 },

	{ X86_FEATURE_BMEC,			CPUID_EBX,  3, 0x80000020, 0 },

	{ X86_FEATURE_ABMC,			CPUID_EBX,  5, 0x80000020, 0 },

	{ X86_FEATURE_SDCIAE,			CPUID_EBX,  6, 0x80000020, 0 },

	{ X86_FEATURE_TSA_SQ_NO,		CPUID_ECX,  1, 0x80000021, 0 },

	{ X86_FEATURE_TSA_L1_NO,		CPUID_ECX,  2, 0x80000021, 0 },

	{ X86_FEATURE_AMD_WORKLOAD_CLASS,	CPUID_EAX, 22, 0x80000021, 0 },