Commit 37f0f245 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
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ARM: dts: qcom: sdx55: Add support for A7 PLL clock 



On SDX55 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210408170457.91409-2-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 885aae68

arch/arm/boot/dts/qcom-sdx55.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -352,6 +352,14 @@ intc: interrupt-controller@17800000 { 
			      <0x17802000 0x1000>;

		};



		a7pll: clock@17808000 {

			compatible = "qcom,sdx55-a7pll";

			reg = <0x17808000 0x1000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "bi_tcxo";

			#clock-cells = <0>;

		};



		watchdog@17817000 {

			compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";

			reg = <0x17817000 0x1000>;