Commit 382cf35f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.19-2022-06-22' of... 

Merge tag 'amd-drm-fixes-5.19-2022-06-22' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.19-2022-06-22:

amdgpu:
- Adjust GTT size logic
- eDP fix for RMB
- DCN 3.15 fix
- DP training fix
- Color encoding fix for DCN2+

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622214106.5984-1-alexander.deucher@amd.com
parents a111daf0 e84131a8

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+14 −6
Original line number Diff line number Diff line
@@ -1798,18 +1798,26 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) 
	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",

		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));



	/* Compute GTT size, either bsaed on 3/4th the size of RAM size

	/* Compute GTT size, either based on 1/2 the size of RAM size

	 * or whatever the user passed on module init */

	if (amdgpu_gtt_size == -1) {

		struct sysinfo si;



		si_meminfo(&si);

		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),

			       adev->gmc.mc_vram_size),

			       ((uint64_t)si.totalram * si.mem_unit * 3/4));

	}

	else

		/* Certain GL unit tests for large textures can cause problems

		 * with the OOM killer since there is no way to link this memory

		 * to a process.  This was originally mitigated (but not necessarily

		 * eliminated) by limiting the GTT size.  The problem is this limit

		 * is often too low for many modern games so just make the limit 1/2

		 * of system memory which aligns with TTM. The OOM accounting needs

		 * to be addressed, but we shouldn't prevent common 3D applications

		 * from being usable just to potentially mitigate that corner case.

		 */

		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),

			       (u64)si.totalram * si.mem_unit / 2);

	} else {

		gtt_size = (uint64_t)amdgpu_gtt_size << 20;

	}



	/* Initialize GTT memory pool */

	r = amdgpu_gtt_mgr_init(adev, gtt_size);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -550,7 +550,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params( 
		if (!bw_params->clk_table.entries[i].dtbclk_mhz)

			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;

	}

	ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz);

	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);

	bw_params->vram_type = bios_info->memory_type;

	bw_params->num_channels = bios_info->ma_channel_number;

	if (!bw_params->num_channels)

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -944,7 +944,7 @@ static void override_lane_settings(const struct link_training_settings *lt_setti 


		return;



	for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {

	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

		if (lt_settings->voltage_swing)

			lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;

		if (lt_settings->pre_emphasis)

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+2 −22
Original line number Diff line number Diff line
@@ -1766,29 +1766,9 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 
				break;

			}

		}



		/*

		 * TO-DO: So far the code logic below only addresses single eDP case.

		 * For dual eDP case, there are a few things that need to be

		 * implemented first:

		 *

		 * 1. Change the fastboot logic above, so eDP link[0 or 1]'s

		 * stream[0 or 1] will all be checked.

		 *

		 * 2. Change keep_edp_vdd_on to an array, and maintain keep_edp_vdd_on

		 * for each eDP.

		 *

		 * Once above 2 things are completed, we can then change the logic below

		 * correspondingly, so dual eDP case will be fully covered.

		 */



		// We are trying to enable eDP, don't power down VDD if eDP stream is existing

		if ((edp_stream_num == 1 && edp_streams[0] != NULL) || can_apply_edp_fast_boot) {

		// We are trying to enable eDP, don't power down VDD

		if (can_apply_edp_fast_boot)

			keep_edp_vdd_on = true;

			DC_LOG_EVENT_LINK_TRAINING("Keep eDP Vdd on\n");

		} else {

			DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, turn eDP Vdd off\n");

		}

	}



	// Check seamless boot support

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c

+3 −0
Original line number Diff line number Diff line
@@ -212,6 +212,9 @@ static void dpp2_cnv_setup ( 
		break;

	}



	/* Set default color space based on format if none is given. */

	color_space = input_color_space ? input_color_space : color_space;



	if (is_2bit == 1 && alpha_2bit_lut != NULL) {

		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);

		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);