Commit 383d0fb8 authored by Gregory Fuchedgi's avatar Gregory Fuchedgi Committed by Jakub Kicinski
Browse files

amd-xgbe: fix PTP addend overflow causing frozen clock



XGBE_PTP_ACT_CLK_FREQ and XGBE_V2_PTP_ACT_CLK_FREQ were 10x too
large (500MHz/1GHz instead of 50MHz/100MHz), causing the computed
addend to overflow the 32-bit tstamp_addend. In the general case
this would result in the clock advancing at the wrong rate. For v2
(PCI), ptpclk_rate is hardcoded to 125MHz, so the addend formula
(ACT_CLK_FREQ << 32) / ptpclk_rate yields exactly 8 * 2^32, and
when stored to the 32-bit tstamp_addend the value is zero. With
addend = 0 the hardware accumulator never overflows and the PTP
clock is fully stopped. For v1 (platform), ptpclk_rate is read from
ACPI/DT so the exact overflow behavior depends on the
firmware-reported frequency.

Define the constants as NSEC_PER_SEC / SSINC so the relationship is
explicit and cannot drift out of sync.

Fixes: fbd47be0 ("amd-xgbe: add hardware PTP timestamping support")
Tested-by: default avatarGregory Fuchedgi <gfuchedgi@gmail.com>
Signed-off-by: default avatarGregory Fuchedgi <gfuchedgi@gmail.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260429-fix-xgbe-ptp-addend-v1-1-fca5b0ca5e62@gmail.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 851bba80
Loading
Loading
Loading
Loading
+2 −2
Original line number Diff line number Diff line
@@ -135,11 +135,11 @@
 */
#define XGBE_TSTAMP_SSINC	20
#define XGBE_TSTAMP_SNSINC	0
#define XGBE_PTP_ACT_CLK_FREQ	500000000
#define XGBE_PTP_ACT_CLK_FREQ	(NSEC_PER_SEC / XGBE_TSTAMP_SSINC)

#define XGBE_V2_TSTAMP_SSINC	0xA
#define XGBE_V2_TSTAMP_SNSINC	0
#define XGBE_V2_PTP_ACT_CLK_FREQ	1000000000
#define XGBE_V2_PTP_ACT_CLK_FREQ	(NSEC_PER_SEC / XGBE_V2_TSTAMP_SSINC)

/* Define maximum supported values */
#define XGBE_MAX_PPS_OUT	4