Commit 3855f1d9 authored by Marek Olšák's avatar Marek Olšák Committed by Alex Deucher
Browse files

drm/amd/display: allow 256B DCC max compressed block sizes on gfx12 



The hw supports it.

Signed-off-by: default avatarMarek Olšák <marek.olsak@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 236f475d

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -122,9 +122,10 @@ 
 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)

 * - 3.61.0 - Contains fix for RV/PCO compute queues

 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT

 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	62

#define KMS_DRIVER_MINOR	63

#define KMS_DRIVER_PATCHLEVEL	0



/*

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -700,7 +700,7 @@ static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, 
	uint64_t mod_4k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_4K_2D);

	uint64_t mod_256b = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256B_2D);

	uint64_t dcc = ver | AMD_FMT_MOD_SET(DCC, 1);

	uint8_t max_comp_block[] = {1, 0};

	uint8_t max_comp_block[] = {2, 1, 0};

	uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0};

	uint8_t i = 0, j = 0;

	uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b, DRM_FORMAT_MOD_LINEAR};