Commit 387f269e authored by Mitul Golani's avatar Mitul Golani Committed by Ankit Nautiyal
Browse files

drm/i915/vrr: Compute vrr.vsync_{start, end} during full modeset 



vrr.vsync_{start,end} computation should not depend on
crtc_state->vrr.enable.

--v1:
 - Explain commit message more clearly [Jani]
 - Instead of tweaking to fastset use vrr.flipline while computing AS_SDP.
--v2:
 - Correct computation of vrr.vsync_start/end should not depend on
   vrr.enable.[ville]
 - vrr enable disable requirement should not obstruct by SDP enable
   disable requirements. [Ville]
--v3:
 - Create separate patch for crtc_state_dump [Ankit].

--v4:
 - Update commit message and header [Ankit].

Signed-off-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250130051609.1796524-3-mitulkumar.ajitkumar.golani@intel.com
parent 2dbbbc17

drivers/gpu/drm/i915/display/intel_vrr.c

+10 −15
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 
		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

	}



	if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) {

	if (HAS_AS_SDP(display)) {

		crtc_state->vrr.vsync_start =

			(crtc_state->hw.adjusted_mode.crtc_vtotal -

			 crtc_state->hw.adjusted_mode.vsync_start);
@@ -388,6 +388,12 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 
		       trans_vrr_ctl(crtc_state));

	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),

		       crtc_state->vrr.flipline - 1);



	if (HAS_AS_SDP(display))

		intel_de_write(display,

			       TRANS_VRR_VSYNC(display, cpu_transcoder),

			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |

			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));

}



void intel_vrr_send_push(struct intel_dsb *dsb,
@@ -432,12 +438,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) 
	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),

		       TRANS_PUSH_EN);



	if (HAS_AS_SDP(display))

		intel_de_write(display,

			       TRANS_VRR_VSYNC(display, cpu_transcoder),

			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |

			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));



	if (crtc_state->cmrr.enable) {

		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

			       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
@@ -462,10 +462,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 
				TRANS_VRR_STATUS(display, cpu_transcoder),

				VRR_STATUS_VRR_EN_LIVE, 1000);

	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);



	if (HAS_AS_SDP(display))

		intel_de_write(display,

			       TRANS_VRR_VSYNC(display, cpu_transcoder), 0);

}



void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
@@ -505,10 +501,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) 
						     TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;

		crtc_state->vrr.vmin = intel_de_read(display,

						     TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;

	}



	if (crtc_state->vrr.enable) {

		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;



		if (HAS_AS_SDP(display)) {

			trans_vrr_vsync =
@@ -520,4 +512,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) 
				REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);

		}

	}



	if (crtc_state->vrr.enable)

		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

}