Commit 38a64e3a authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add C2PMSG_109/126 reg field shift/masks 



Add MP0_C2PMSG_109/126 register field shift/masks
that are used to identify boot status by driver.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Reviewed-by: default avatarLe Ma <le.ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dbab6356

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h

+28 −0
Original line number Diff line number Diff line
@@ -242,6 +242,34 @@ 
//MP0_SMN_C2PMSG_103

#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0

#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL

//MP0_SMN_C2PMSG_109

#define MP0_SMN_C2PMSG_109__CONTENT__SHIFT                                                                    0x0

#define MP0_SMN_C2PMSG_109__CONTENT_MASK                                                                      0xFFFFFFFFL

//MP0_SMN_C2PMSG_126

#define MP0_SMN_C2PMSG_126__GPU_ERR_MEM_TRAINING__SHIFT                                                       0x0

#define MP0_SMN_C2PMSG_126__GPU_ERR_FW_LOAD__SHIFT                                                            0x1

#define MP0_SMN_C2PMSG_126__GPU_ERR_WAFL_LINK_TRAINING__SHIFT                                                 0x2

#define MP0_SMN_C2PMSG_126__GPU_ERR_XGMI_LINK_TRAINING__SHIFT                                                 0x3

#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_CP_LINK_TRAINING__SHIFT                                               0x4

#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_DP_LINK_TRAINING__SHIFT                                               0x5

#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_MEM_TEST__SHIFT                                                       0x6

#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_BIST_TEST__SHIFT                                                      0x7

#define MP0_SMN_C2PMSG_126__SOCKET_ID__SHIFT                                                                  0x8

#define MP0_SMN_C2PMSG_126__AID_ID__SHIFT                                                                     0xb

#define MP0_SMN_C2PMSG_126__HBM_ID__SHIFT                                                                     0xd

#define MP0_SMN_C2PMSG_126__BOOT_STATUS__SHIFT                                                                0x1f

#define MP0_SMN_C2PMSG_126__GPU_ERR_MEM_TRAINING_MASK                                                         0x00000001L

#define MP0_SMN_C2PMSG_126__GPU_ERR_FW_LOAD_MASK                                                              0x00000002L

#define MP0_SMN_C2PMSG_126__GPU_ERR_WAFL_LINK_TRAINING_MASK                                                   0x00000004L

#define MP0_SMN_C2PMSG_126__GPU_ERR_XGMI_LINK_TRAINING_MASK                                                   0x00000008L

#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_CP_LINK_TRAINING_MASK                                                 0x00000010L

#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_DP_LINK_TRAINING_MASK                                                 0x00000020L

#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_MEM_TEST_MASK                                                         0x00000040L

#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_BIST_TEST_MASK                                                        0x00000080L

#define MP0_SMN_C2PMSG_126__SOCKET_ID_MASK                                                                    0x00000700L

#define MP0_SMN_C2PMSG_126__AID_ID_MASK                                                                       0x00001800L

#define MP0_SMN_C2PMSG_126__HBM_ID_MASK                                                                       0x00002000L

#define MP0_SMN_C2PMSG_126__BOOT_STATUS_MASK                                                                  0x80000000L

//MP0_SMN_IH_CREDIT

#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0

#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10