Commit 38bafa65 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-12-08' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular weekly fixes, mostly amdgpu and i915 as usual. A couple of
  nouveau, panfrost, one core and one bridge Kconfig.

  Seems about normal for rc5.

  atomic-helpers:
   - invoke end_fb_access while owning plane state

  i915:
   - fix a missing dep for a previous fix
   - Relax BXT/GLK DSI transcoder hblank limits
   - Fix DP MST .mode_valid_ctx() return values
   - Reject DP MST modes that require bigjoiner (as it's not yet
     supported on DP MST)
   - Fix _intel_dsb_commit() variable type to allow negative values

  nouveau:
   - document some bits of gsp rm
   - flush vmm more on tu102 to avoid hangs

  panfrost:
   - fix imported dma-buf objects residency
   - fix device freq update

  bridge:
   - tc358768 - fix Kconfig

  amdgpu:
   - Disable MCBP on gfx9
   - DC vbios fix
   - eDP fix
   - dml2 UBSAN fix
   - SMU 14 fix
   - RAS fixes
   - dml KASAN/KCSAN fix
   - PSP 13 fix
   - Clockgating fixes
   - Suspend fix

  exynos:
   - fix pointer dereference
   - fix wrong error check"

* tag 'drm-fixes-2023-12-08' of git://anongit.freedesktop.org/drm/drm: (27 commits)
  drm/exynos: fix a wrong error checking
  drm/exynos: fix a potential error pointer dereference
  drm/amdgpu: fix buffer funcs setting order on suspend
  drm/amdgpu: Avoid querying DRM MGCG status
  drm/amdgpu: Update HDP 4.4.2 clock gating flags
  drm/amdgpu: Add NULL checks for function pointers
  drm/amdgpu: Restrict extended wait to PSP v13.0.6
  drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml
  drm/amdgpu: optimize the printing order of error data
  drm/amdgpu: Update fw version for boot time error query
  drm/amd/pm: support new mca smu error code decoding
  drm/amd/swsmu: update smu v14_0_0 driver if version and metrics table
  drm/amd/display: Fix array-index-out-of-bounds in dml2
  drm/amd/display: Add monitor patch for specific eDP
  drm/amd/display: Use channel_width = 2 for vram table 3.0
  drm/amdgpu: disable MCBP by default
  drm/atomic-helpers: Invoke end_fb_access while owning plane state
  drm/i915: correct the input parameter on _intel_dsb_commit()
  drm/i915/mst: Reject modes that require the bigjoiner
  drm/i915/mst: Fix .mode_valid_ctx() return values
  ...
parents 4df7c5fd b7b5a56a

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −4
Original line number Diff line number Diff line
@@ -3791,10 +3791,6 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev) 
		adev->gfx.mcbp = true;

	else if (amdgpu_mcbp == 0)

		adev->gfx.mcbp = false;

	else if ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 0, 0)) &&

		 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 0, 0)) &&

		 adev->gfx.num_gfx_rings)

		adev->gfx.mcbp = true;



	if (amdgpu_sriov_vf(adev))

		adev->gfx.mcbp = true;
@@ -4531,6 +4527,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 
	if (r)

		return r;



	amdgpu_ttm_set_buffer_funcs_status(adev, false);



	amdgpu_fence_driver_hw_fini(adev);



	amdgpu_device_ip_suspend_phase2(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define MCA_REG__STATUS__ERRORCODEEXT(x)	MCA_REG_FIELD(x, 21, 16)

#define MCA_REG__STATUS__ERRORCODE(x)		MCA_REG_FIELD(x, 15, 0)



#define MCA_REG__SYND__ERRORINFORMATION(x)	MCA_REG_FIELD(x, 17, 0)



enum amdgpu_mca_ip {

	AMDGPU_MCA_IP_UNKNOW = -1,

	AMDGPU_MCA_IP_PSP = 0,

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+17 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <linux/reboot.h>

#include <linux/syscalls.h>

#include <linux/pm_runtime.h>

#include <linux/list_sort.h>



#include "amdgpu.h"

#include "amdgpu_ras.h"
@@ -3665,6 +3666,21 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void) 
	return err_node;

}



static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)

{

	struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);

	struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);

	struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;

	struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;



	if (unlikely(infoa->socket_id != infob->socket_id))

		return infoa->socket_id - infob->socket_id;

	else

		return infoa->die_id - infob->die_id;



	return 0;

}



static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,

						      struct amdgpu_smuio_mcm_config_info *mcm_info)

{
@@ -3682,6 +3698,7 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d 


	err_data->err_list_count++;

	list_add_tail(&err_node->node, &err_data->err_node_list);

	list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);



	return &err_node->err_info;

}

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

+5 −0
Original line number Diff line number Diff line
@@ -129,6 +129,11 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, 
{

	int data;



	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) {

		/* Default enabled */

		*flags |= AMD_CG_SUPPORT_HDP_MGCG;

		return;

	}

	/* AMD_CG_SUPPORT_HDP_LS */

	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));

	if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

+8 −4
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 
#define GFX_CMD_USB_PD_USE_LFB 0x480



/* Retry times for vmbx ready wait */

#define PSP_VMBX_POLLING_LIMIT 20000

#define PSP_VMBX_POLLING_LIMIT 3000



/* VBIOS gfl defines */

#define MBOX_READY_MASK 0x80000000
@@ -161,14 +161,18 @@ static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 
static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;

	int retry_loop, ret;

	int retry_loop, retry_cnt, ret;



	retry_cnt =

		(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?

			PSP_VMBX_POLLING_LIMIT :

			10;

	/* Wait for bootloader to signify that it is ready having bit 31 of

	 * C2PMSG_35 set to 1. All other bits are expected to be cleared.

	 * If there is an error in processing command, bits[7:0] will be set.

	 * This is applicable for PSP v13.0.6 and newer.

	 */

	for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {

	for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),

			0x80000000, 0xffffffff, false);
@@ -821,7 +825,7 @@ static int psp_v13_0_query_boot_status(struct psp_context *psp) 
	if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))

		return 0;



	if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10007)

	if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10109)

		return 0;



	for_each_inst(i, inst_mask) {