Commit 396f45a3 authored by Andy Shevchenko's avatar Andy Shevchenko
Browse files

Merge patch series "pinctrl: intel: Consolidate struct intel_padgroup initialisers" 

Andy Shevchenko <andriy.shevchenko@linux.intel.com> says:

We have plenty of repetitive *_GPP() macros across the drivers.
Consolidate them under a newly introduced INTEL_GPP().

Link: https://patch.msgid.link/20251104145814.1018867-1-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
parents ce272781 d99b7a9d

drivers/pinctrl/intel/pinctrl-alderlake.c

+30 −38
Original line number Diff line number Diff line
@@ -27,14 +27,6 @@ 
#define ADL_S_GPI_IS		0x200

#define ADL_S_GPI_IE		0x220



#define ADL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



#define ADL_N_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
@@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = { 
};



static const struct intel_padgroup adln_community0_gpps[] = {

	ADL_GPP(0, 0, 25, 0),				/* GPP_B */

	ADL_GPP(1, 26, 41, 32),				/* GPP_T */

	ADL_GPP(2, 42, 66, 64),				/* GPP_A */

	INTEL_GPP(0, 0, 25, 0),				/* GPP_B */

	INTEL_GPP(1, 26, 41, 32),			/* GPP_T */

	INTEL_GPP(2, 42, 66, 64),			/* GPP_A */

};



static const struct intel_padgroup adln_community1_gpps[] = {

	ADL_GPP(0, 67, 74, 96),				/* GPP_S */

	ADL_GPP(1, 75, 94, 128),			/* GPP_I */

	ADL_GPP(2, 95, 118, 160),			/* GPP_H */

	ADL_GPP(3, 119, 139, 192),			/* GPP_D */

	ADL_GPP(4, 140, 168, 224),			/* vGPIO */

	INTEL_GPP(0, 67, 74, 96),			/* GPP_S */

	INTEL_GPP(1, 75, 94, 128),			/* GPP_I */

	INTEL_GPP(2, 95, 118, 160),			/* GPP_H */

	INTEL_GPP(3, 119, 139, 192),			/* GPP_D */

	INTEL_GPP(4, 140, 168, 224),			/* vGPIO */

};



static const struct intel_padgroup adln_community4_gpps[] = {

	ADL_GPP(0, 169, 192, 256),			/* GPP_C */

	ADL_GPP(1, 193, 217, 288),			/* GPP_F */

	ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	ADL_GPP(3, 224, 248, 320),			/* GPP_E */

	INTEL_GPP(0, 169, 192, 256),			/* GPP_C */

	INTEL_GPP(1, 193, 217, 288),			/* GPP_F */

	INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(3, 224, 248, 320),			/* GPP_E */

};



static const struct intel_padgroup adln_community5_gpps[] = {

	ADL_GPP(0, 249, 256, 352),			/* GPP_R */

	INTEL_GPP(0, 249, 256, 352),			/* GPP_R */

};



static const struct intel_community adln_communities[] = {
@@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = { 
};



static const struct intel_padgroup adls_community0_gpps[] = {

	ADL_GPP(0, 0, 24, 0),				/* GPP_I */

	ADL_GPP(1, 25, 47, 32),				/* GPP_R */

	ADL_GPP(2, 48, 59, 64),				/* GPP_J */

	ADL_GPP(3, 60, 86, 96),				/* vGPIO */

	ADL_GPP(4, 87, 94, 128),			/* vGPIO_0 */

	INTEL_GPP(0, 0, 24, 0),				/* GPP_I */

	INTEL_GPP(1, 25, 47, 32),			/* GPP_R */

	INTEL_GPP(2, 48, 59, 64),			/* GPP_J */

	INTEL_GPP(3, 60, 86, 96),			/* vGPIO */

	INTEL_GPP(4, 87, 94, 128),			/* vGPIO_0 */

};



static const struct intel_padgroup adls_community1_gpps[] = {

	ADL_GPP(0, 95, 118, 160),			/* GPP_B */

	ADL_GPP(1, 119, 126, 192),			/* GPP_G */

	ADL_GPP(2, 127, 150, 224),			/* GPP_H */

	INTEL_GPP(0, 95, 118, 160),			/* GPP_B */

	INTEL_GPP(1, 119, 126, 192),			/* GPP_G */

	INTEL_GPP(2, 127, 150, 224),			/* GPP_H */

};



static const struct intel_padgroup adls_community3_gpps[] = {

	ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP),	/* SPI0 */

	ADL_GPP(1, 160, 175, 256),			/* GPP_A */

	ADL_GPP(2, 176, 199, 288),			/* GPP_C */

	INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP),	/* SPI0 */

	INTEL_GPP(1, 160, 175, 256),			/* GPP_A */

	INTEL_GPP(2, 176, 199, 288),			/* GPP_C */

};



static const struct intel_padgroup adls_community4_gpps[] = {

	ADL_GPP(0, 200, 207, 320),			/* GPP_S */

	ADL_GPP(1, 208, 230, 352),			/* GPP_E */

	ADL_GPP(2, 231, 245, 384),			/* GPP_K */

	ADL_GPP(3, 246, 269, 416),			/* GPP_F */

	INTEL_GPP(0, 200, 207, 320),			/* GPP_S */

	INTEL_GPP(1, 208, 230, 352),			/* GPP_E */

	INTEL_GPP(2, 231, 245, 384),			/* GPP_K */

	INTEL_GPP(3, 246, 269, 416),			/* GPP_F */

};



static const struct intel_padgroup adls_community5_gpps[] = {

	ADL_GPP(0, 270, 294, 448),			/* GPP_D */

	ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(0, 270, 294, 448),			/* GPP_D */

	INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

};



static const struct intel_community adls_communities[] = {

drivers/pinctrl/intel/pinctrl-cannonlake.c

+30 −38
Original line number Diff line number Diff line
@@ -28,14 +28,6 @@ 
#define CNL_H_GPI_IS		0x100

#define CNL_H_GPI_IE		0x120



#define CNL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



#define CNL_LP_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = { 
};



static const struct intel_padgroup cnlh_community0_gpps[] = {

	CNL_GPP(0, 0, 24, 0),			/* GPP_A */

	CNL_GPP(1, 25, 50, 32),			/* GPP_B */

	INTEL_GPP(0, 0, 24, 0),				/* GPP_A */

	INTEL_GPP(1, 25, 50, 32),			/* GPP_B */

};



static const struct intel_padgroup cnlh_community1_gpps[] = {

	CNL_GPP(0, 51, 74, 64),				/* GPP_C */

	CNL_GPP(1, 75, 98, 96),				/* GPP_D */

	CNL_GPP(2, 99, 106, 128),			/* GPP_G */

	CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP),	/* AZA */

	CNL_GPP(4, 115, 146, 160),			/* vGPIO_0 */

	CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP),	/* vGPIO_1 */

	INTEL_GPP(0, 51, 74, 64),			/* GPP_C */

	INTEL_GPP(1, 75, 98, 96),			/* GPP_D */

	INTEL_GPP(2, 99, 106, 128),			/* GPP_G */

	INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP),	/* AZA */

	INTEL_GPP(4, 115, 146, 160),			/* vGPIO_0 */

	INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP),	/* vGPIO_1 */

};



static const struct intel_padgroup cnlh_community3_gpps[] = {

	CNL_GPP(0, 155, 178, 192),			/* GPP_K */

	CNL_GPP(1, 179, 202, 224),			/* GPP_H */

	CNL_GPP(2, 203, 215, 256),			/* GPP_E */

	CNL_GPP(3, 216, 239, 288),			/* GPP_F */

	CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(0, 155, 178, 192),			/* GPP_K */

	INTEL_GPP(1, 179, 202, 224),			/* GPP_H */

	INTEL_GPP(2, 203, 215, 256),			/* GPP_E */

	INTEL_GPP(3, 216, 239, 288),			/* GPP_F */

	INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP),	/* SPI */

};



static const struct intel_padgroup cnlh_community4_gpps[] = {

	CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP),	/* CPU */

	CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	CNL_GPP(2, 269, 286, 320),			/* GPP_I */

	CNL_GPP(3, 287, 298, 352),			/* GPP_J */

	INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP),	/* CPU */

	INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(2, 269, 286, 320),			/* GPP_I */

	INTEL_GPP(3, 287, 298, 352),			/* GPP_J */

};



static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = { 
};



static const struct intel_padgroup cnllp_community0_gpps[] = {

	CNL_GPP(0, 0, 24, 0),				/* GPP_A */

	CNL_GPP(1, 25, 50, 32),				/* GPP_B */

	CNL_GPP(2, 51, 58, 64),				/* GPP_G */

	CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(0, 0, 24, 0),				/* GPP_A */

	INTEL_GPP(1, 25, 50, 32),			/* GPP_B */

	INTEL_GPP(2, 51, 58, 64),			/* GPP_G */

	INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP),	/* SPI */

};



static const struct intel_padgroup cnllp_community1_gpps[] = {

	CNL_GPP(0, 68, 92, 96),				/* GPP_D */

	CNL_GPP(1, 93, 116, 128),			/* GPP_F */

	CNL_GPP(2, 117, 140, 160),			/* GPP_H */

	CNL_GPP(3, 141, 172, 192),			/* vGPIO */

	CNL_GPP(4, 173, 180, 224),			/* vGPIO */

	INTEL_GPP(0, 68, 92, 96),			/* GPP_D */

	INTEL_GPP(1, 93, 116, 128),			/* GPP_F */

	INTEL_GPP(2, 117, 140, 160),			/* GPP_H */

	INTEL_GPP(3, 141, 172, 192),			/* vGPIO */

	INTEL_GPP(4, 173, 180, 224),			/* vGPIO */

};



static const struct intel_padgroup cnllp_community4_gpps[] = {

	CNL_GPP(0, 181, 204, 256),			/* GPP_C */

	CNL_GPP(1, 205, 228, 288),			/* GPP_E */

	CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(0, 181, 204, 256),			/* GPP_C */

	INTEL_GPP(1, 205, 228, 288),			/* GPP_E */

	INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

};



static const struct intel_community cnllp_communities[] = {

drivers/pinctrl/intel/pinctrl-icelake.c

+26 −34
Original line number Diff line number Diff line
@@ -28,14 +28,6 @@ 
#define ICL_N_GPI_IS		0x100

#define ICL_N_GPI_IE		0x120



#define ICL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



#define ICL_LP_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
@@ -302,29 +294,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = { 
};



static const struct intel_padgroup icllp_community0_gpps[] = {

	ICL_GPP(0, 0, 7, 0),				/* GPP_G */

	ICL_GPP(1, 8, 33, 32),				/* GPP_B */

	ICL_GPP(2, 34, 58, 64),				/* GPP_A */

	INTEL_GPP(0, 0, 7, 0),				/* GPP_G */

	INTEL_GPP(1, 8, 33, 32),			/* GPP_B */

	INTEL_GPP(2, 34, 58, 64),			/* GPP_A */

};



static const struct intel_padgroup icllp_community1_gpps[] = {

	ICL_GPP(0, 59, 82, 96),				/* GPP_H */

	ICL_GPP(1, 83, 103, 128),			/* GPP_D */

	ICL_GPP(2, 104, 123, 160),			/* GPP_F */

	ICL_GPP(3, 124, 152, 192),			/* vGPIO */

	INTEL_GPP(0, 59, 82, 96),			/* GPP_H */

	INTEL_GPP(1, 83, 103, 128),			/* GPP_D */

	INTEL_GPP(2, 104, 123, 160),			/* GPP_F */

	INTEL_GPP(3, 124, 152, 192),			/* vGPIO */

};



static const struct intel_padgroup icllp_community4_gpps[] = {

	ICL_GPP(0, 153, 176, 224),			/* GPP_C */

	ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	ICL_GPP(2, 183, 206, 256),			/* GPP_E */

	ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(0, 153, 176, 224),			/* GPP_C */

	INTEL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(2, 183, 206, 256),			/* GPP_E */

	INTEL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

};



static const struct intel_padgroup icllp_community5_gpps[] = {

	ICL_GPP(0, 216, 223, 288),			/* GPP_R */

	ICL_GPP(1, 224, 231, 320),			/* GPP_S */

	ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(0, 216, 223, 288),			/* GPP_R */

	INTEL_GPP(1, 224, 231, 320),			/* GPP_S */

	INTEL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP),	/* SPI */

};



static const struct intel_community icllp_communities[] = {
@@ -632,27 +624,27 @@ static const struct pinctrl_pin_desc icln_pins[] = { 
};



static const struct intel_padgroup icln_community0_gpps[] = {

	ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	ICL_GPP(1, 9, 34, 32),				/* GPP_B */

	ICL_GPP(2, 35, 55, 64),				/* GPP_A */

	ICL_GPP(3, 56, 63, 96),				/* GPP_S */

	ICL_GPP(4, 64, 71, 128),			/* GPP_R */

	INTEL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(1, 9, 34, 32),			/* GPP_B */

	INTEL_GPP(2, 35, 55, 64),			/* GPP_A */

	INTEL_GPP(3, 56, 63, 96),			/* GPP_S */

	INTEL_GPP(4, 64, 71, 128),			/* GPP_R */

};



static const struct intel_padgroup icln_community1_gpps[] = {

	ICL_GPP(0, 72, 95, 160),			/* GPP_H */

	ICL_GPP(1, 96, 121, 192),			/* GPP_D */

	ICL_GPP(2, 122, 150, 224),			/* vGPIO */

	ICL_GPP(3, 151, 174, 256),			/* GPP_C */

	INTEL_GPP(0, 72, 95, 160),			/* GPP_H */

	INTEL_GPP(1, 96, 121, 192),			/* GPP_D */

	INTEL_GPP(2, 122, 150, 224),			/* vGPIO */

	INTEL_GPP(3, 151, 174, 256),			/* GPP_C */

};



static const struct intel_padgroup icln_community4_gpps[] = {

	ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	ICL_GPP(1, 181, 204, 288),			/* GPP_E */

	INTEL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(1, 181, 204, 288),			/* GPP_E */

};



static const struct intel_padgroup icln_community5_gpps[] = {

	ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO),	/* GPP_G */

	INTEL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO),	/* GPP_G */

};



static const struct intel_community icln_communities[] = {

drivers/pinctrl/intel/pinctrl-intel.h

+9 −0
Original line number Diff line number Diff line
@@ -76,6 +76,15 @@ enum { 
	INTEL_GPIO_BASE_MATCH	= 0,

};



/* Initialise struct intel_padgroup */

#define INTEL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



/**

 * struct intel_community - Intel pin community description

 * @barno: MMIO BAR number where registers for this community reside

drivers/pinctrl/intel/pinctrl-jasperlake.c

+13 −21
Original line number Diff line number Diff line
@@ -21,14 +21,6 @@ 
#define JSL_GPI_IS	0x100

#define JSL_GPI_IE	0x120



#define JSL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



#define JSL_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
@@ -283,28 +275,28 @@ static const struct pinctrl_pin_desc jsl_pins[] = { 
};



static const struct intel_padgroup jsl_community0_gpps[] = {

	JSL_GPP(0, 0, 19, 320),				/* GPP_F */

	JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	JSL_GPP(2, 29, 54, 32),				/* GPP_B */

	JSL_GPP(3, 55, 75, 64),				/* GPP_A */

	JSL_GPP(4, 76, 83, 96),				/* GPP_S */

	JSL_GPP(5, 84, 91, 128),			/* GPP_R */

	INTEL_GPP(0, 0, 19, 320),			/* GPP_F */

	INTEL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(2, 29, 54, 32),			/* GPP_B */

	INTEL_GPP(3, 55, 75, 64),			/* GPP_A */

	INTEL_GPP(4, 76, 83, 96),			/* GPP_S */

	INTEL_GPP(5, 84, 91, 128),			/* GPP_R */

};



static const struct intel_padgroup jsl_community1_gpps[] = {

	JSL_GPP(0, 92, 115, 160),			/* GPP_H */

	JSL_GPP(1, 116, 141, 192),			/* GPP_D */

	JSL_GPP(2, 142, 170, 224),			/* vGPIO */

	JSL_GPP(3, 171, 194, 256),			/* GPP_C */

	INTEL_GPP(0, 92, 115, 160),			/* GPP_H */

	INTEL_GPP(1, 116, 141, 192),			/* GPP_D */

	INTEL_GPP(2, 142, 170, 224),			/* vGPIO */

	INTEL_GPP(3, 171, 194, 256),			/* GPP_C */

};



static const struct intel_padgroup jsl_community4_gpps[] = {

	JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	JSL_GPP(1, 201, 224, 288),			/* GPP_E */

	INTEL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(1, 201, 224, 288),			/* GPP_E */

};



static const struct intel_padgroup jsl_community5_gpps[] = {

	JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO),	/* GPP_G */

	INTEL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO),	/* GPP_G */

};



static const struct intel_community jsl_communities[] = {