Commit 397411c7 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Handle PSB CSYNC traps 



The architecture introduces a trap for PSB CSYNC that fits in
 the same EC as LS64. Let's deal with it in a similar way as
LS64.

It's not that we expect this to be useful any time soon anyway.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent ef6d7d26

arch/arm64/include/asm/esr.h

+2 −1
Original line number Diff line number Diff line
@@ -182,10 +182,11 @@ 
#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)

#define ESR_ELx_xVC_IMM_MASK	((UL(1) << 16) - 1)



/* ISS definitions for LD64B/ST64B instructions */

/* ISS definitions for LD64B/ST64B/PSBCSYNC instructions */

#define ESR_ELx_ISS_OTHER_ST64BV	(0)

#define ESR_ELx_ISS_OTHER_ST64BV0	(1)

#define ESR_ELx_ISS_OTHER_LDST64B	(2)

#define ESR_ELx_ISS_OTHER_PSBCSYNC	(4)



#define DISR_EL1_IDS		(UL(1) << 24)

/*

arch/arm64/kvm/emulate-nested.c

+1 −0
Original line number Diff line number Diff line
@@ -2000,6 +2000,7 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 
 * trap is handled somewhere else.

 */

static const union trap_config non_0x18_fgt[] __initconst = {

	FGT(HFGITR, PSBCSYNC, 1),

	FGT(HFGITR, nGCSSTR_EL1, 0),

	FGT(HFGITR, SVC_EL1, 1),

	FGT(HFGITR, SVC_EL0, 1),

arch/arm64/kvm/handle_exit.c

+5 −0
Original line number Diff line number Diff line
@@ -347,6 +347,11 @@ static int handle_other(struct kvm_vcpu *vcpu) 
		if (is_l2)

			fwd = !(hcrx & HCRX_EL2_EnALS);

		break;

	case ESR_ELx_ISS_OTHER_PSBCSYNC:

		allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P5);

		if (is_l2)

			fwd = (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_PSBCSYNC);

		break;

	default:

		/* Clearly, we're missing something. */

		WARN_ON_ONCE(1);

arch/arm64/tools/sysreg

+1 −1
Original line number Diff line number Diff line
@@ -3406,7 +3406,7 @@ Field 0 AFSR0_EL1 
EndSysreg



Sysreg HFGITR_EL2	3	4	1	1	6

Res0	63

Field   63	PSBCSYNC

Field	62	ATS1E1A

Res0	61

Field	60	COSPRCTX