Commit 39923050 authored by Ryan Seto's avatar Ryan Seto Committed by Alex Deucher
Browse files

drm/amd/display: Clear DPP 3DLUT Cap 



[WHY & HOW]
Clear DPP 3DLUT Cap flag on ASICs that do not use it

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarRyan Seto <ryanseto@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent da63df07

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -245,6 +245,7 @@ struct mpc_color_caps { 
	struct rom_curve_caps ogam_rom_caps;

	struct lut3d_caps mcm_3d_lut_caps;

	struct lut3d_caps rmcm_3d_lut_caps;

	bool preblend;

};



/**

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -2251,7 +2251,7 @@ static bool dcn32_resource_construct( 
	dc->caps.color.dpp.gamma_corr = 1;

	dc->caps.color.dpp.dgam_rom_for_yuv = 0;



	dc->caps.color.dpp.hw_3d_lut = 1;

	dc->caps.color.dpp.hw_3d_lut = 0;

	dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1

	// no OGAM ROM on DCN2 and later ASICs

	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
@@ -2270,6 +2270,7 @@ static bool dcn32_resource_construct( 
	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;

	dc->caps.color.mpc.preblend = true;



	/* Use pipe context based otg sync logic */

	dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

+3 −2
Original line number Diff line number Diff line
@@ -1755,8 +1755,8 @@ static bool dcn321_resource_construct( 
	dc->caps.color.dpp.gamma_corr = 1;

	dc->caps.color.dpp.dgam_rom_for_yuv = 0;



	dc->caps.color.dpp.hw_3d_lut = 1;

	dc->caps.color.dpp.ogam_ram = 1;

	dc->caps.color.dpp.hw_3d_lut = 0;

	dc->caps.color.dpp.ogam_ram = 0;

	// no OGAM ROM on DCN2 and later ASICs

	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
@@ -1774,6 +1774,7 @@ static bool dcn321_resource_construct( 
	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;

	dc->caps.color.mpc.preblend = true;



	/* Use pipe context based otg sync logic */

	dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -1874,7 +1874,7 @@ static bool dcn35_resource_construct( 
	dc->caps.color.dpp.gamma_corr = 1;

	dc->caps.color.dpp.dgam_rom_for_yuv = 0;



	dc->caps.color.dpp.hw_3d_lut = 1;

	dc->caps.color.dpp.hw_3d_lut = 0;

	dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1

	// no OGAM ROM on DCN301

	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
@@ -1893,6 +1893,7 @@ static bool dcn35_resource_construct( 
	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;

	dc->caps.color.mpc.preblend = true;



	dc->caps.num_of_host_routers = 2;

	dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -1846,7 +1846,7 @@ static bool dcn351_resource_construct( 
	dc->caps.color.dpp.gamma_corr = 1;

	dc->caps.color.dpp.dgam_rom_for_yuv = 0;



	dc->caps.color.dpp.hw_3d_lut = 1;

	dc->caps.color.dpp.hw_3d_lut = 0;

	dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1

	// no OGAM ROM on DCN301

	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
@@ -1865,6 +1865,7 @@ static bool dcn351_resource_construct( 
	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;

	dc->caps.color.mpc.preblend = true;



	dc->caps.num_of_host_routers = 2;

	dc->caps.num_of_dpias_per_host_router = 2;