Commit 39a72b4f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.14-tag1' of... 

Merge tag 'renesas-clk-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver udpates from Geert Uytterhoeven:

 - Add sound (SSI), remaining serial (SCIF), and ADC clocks, resets
   and power domains on Renesas RZ/G3S
 - Add system restart support on Renesas RZ/N1
 - Add camera clocks and resets on Renesas RZ/V2H(P)
 - Add display clocks on Renesas R-Car V4M

* tag 'renesas-clk-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
  clk: renesas: r8a779h0: Add display clocks
  clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
  clk: renesas: rzv2h: Add selective Runtime PM support for clocks
  clk: renesas: r9a06g032: Use BIT macro consistently
  clk: renesas: r9a06g032: Add restart handler
  clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs
  clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI
  clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()
parents d3dcc98f f9627452

drivers/clk/renesas/r8a779h0-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -177,6 +177,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { 
	DEF_MOD("canfd0",	328,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("csi40",	331,	R8A779H0_CLK_CSI),

	DEF_MOD("csi41",	400,	R8A779H0_CLK_CSI),

	DEF_MOD("dis0",		411,	R8A779H0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink0",	415,	R8A779H0_CLK_VIOBUSD2),

	DEF_MOD("fcpvd0",	508,	R8A779H0_CLK_VIOBUSD2),

	DEF_MOD("hscif0",	514,	R8A779H0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779H0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779H0_CLK_SASYNCPERD1),
@@ -225,6 +228,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { 
	DEF_MOD("vin15",	811,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin16",	812,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin17",	813,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vspd0",	830,	R8A779H0_CLK_VIOBUSD2),

	DEF_MOD("wdt1:wdt0",	907,	R8A779H0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779H0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779H0_CLK_R),

drivers/clk/renesas/r9a06g032-clocks.c

+28 −1
Original line number Diff line number Diff line
@@ -20,15 +20,24 @@ 
#include <linux/platform_device.h>

#include <linux/pm_clock.h>

#include <linux/pm_domain.h>

#include <linux/reboot.h>

#include <linux/slab.h>

#include <linux/soc/renesas/r9a06g032-sysctrl.h>

#include <linux/spinlock.h>

#include <dt-bindings/clock/r9a06g032-sysctrl.h>



#define R9A06G032_SYSCTRL_USB    0x00

#define R9A06G032_SYSCTRL_USB_H2MODE  (1<<1)

#define R9A06G032_SYSCTRL_USB_H2MODE BIT(1)

#define R9A06G032_SYSCTRL_DMAMUX 0xA0



#define R9A06G032_SYSCTRL_RSTEN 0x120

#define R9A06G032_SYSCTRL_RSTEN_MRESET_EN BIT(0)

#define R9A06G032_SYSCTRL_RSTCTRL 0x198

/* These work for both reset registers */

#define R9A06G032_SYSCTRL_SWRST BIT(6)

#define R9A06G032_SYSCTRL_WDA7RST_1 BIT(2)

#define R9A06G032_SYSCTRL_WDA7RST_0 BIT(1)



/**

 * struct regbit - describe one bit in a register

 * @reg: offset of register relative to base address,
@@ -1270,6 +1279,12 @@ static void r9a06g032_clocks_del_clk_provider(void *data) 
	of_clk_del_provider(data);

}



static int r9a06g032_restart_handler(struct sys_off_data *data)

{

	writel(R9A06G032_SYSCTRL_SWRST, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTCTRL);

	return NOTIFY_DONE;

}



static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)

{

	struct device_node *usbf_np;
@@ -1324,6 +1339,18 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 


	r9a06g032_init_h2mode(clocks);



	/* Clear potentially pending resets */

	writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,

	       clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);

	/* Allow software reset */

	writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,

	       clocks->reg + R9A06G032_SYSCTRL_RSTEN);



	error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,

					      r9a06g032_restart_handler, NULL);

	if (error)

		dev_warn(dev, "couldn't register restart handler (%d)\n", error);



	for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {

		const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];

		const char *parent_name = d->source ?

drivers/clk/renesas/r9a08g045-cpg.c

+47 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { 
	DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),

	DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),

	DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),

	DEF_FIXED("TSU", R9A08G045_CLK_TSU, CLK_PLL2_DIV2, 1, 8),

};



static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
@@ -209,6 +210,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 
	DEF_MOD("sdhi2_imclk2",		R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),

	DEF_MOD("sdhi2_clk_hs",		R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),

	DEF_MOD("sdhi2_aclk",		R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),

	DEF_MOD("ssi0_pclk2",		R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0),

	DEF_MOD("ssi0_sfr",		R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1),

	DEF_MOD("ssi1_pclk2",		R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2),

	DEF_MOD("ssi1_sfr",		R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3),

	DEF_MOD("ssi2_pclk2",		R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4),

	DEF_MOD("ssi2_sfr",		R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5),

	DEF_MOD("ssi3_pclk2",		R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6),

	DEF_MOD("ssi3_sfr",		R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7),

	DEF_MOD("usb0_host",		R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),

	DEF_MOD("usb1_host",		R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),

	DEF_MOD("usb0_func",		R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
@@ -224,7 +233,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 
	DEF_MOD("i2c2_pclk",		R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),

	DEF_MOD("i2c3_pclk",		R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),

	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),

	DEF_MOD("scif1_clk_pck",	R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1),

	DEF_MOD("scif2_clk_pck",	R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2),

	DEF_MOD("scif3_clk_pck",	R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3),

	DEF_MOD("scif4_clk_pck",	R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),

	DEF_MOD("scif5_clk_pck",	R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),

	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),

	DEF_MOD("adc_adclk",		R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),

	DEF_MOD("adc_pclk",		R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),

	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),

};
@@ -238,6 +254,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = { 
	DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),

	DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),

	DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),

	DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0),

	DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1),

	DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2),

	DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3),

	DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),

	DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),

	DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
@@ -249,9 +269,16 @@ static const struct rzg2l_reset r9a08g045_resets[] = { 
	DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),

	DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),

	DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),

	DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1),

	DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2),

	DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3),

	DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4),

	DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5),

	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),

	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),

	DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),

	DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),

	DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),

	DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),

};
@@ -286,6 +313,14 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 
				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),

	DEF_PD("sdhi2",		R9A08G045_PD_SDHI2,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),

	DEF_PD("ssi0",		R9A08G045_PD_SSI0,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),

	DEF_PD("ssi1",		R9A08G045_PD_SSI1,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),

	DEF_PD("ssi2",		R9A08G045_PD_SSI2,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),

	DEF_PD("ssi3",		R9A08G045_PD_SSI3,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),

	DEF_PD("usb0",		R9A08G045_PD_USB0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),

	DEF_PD("usb1",		R9A08G045_PD_USB1,
@@ -306,6 +341,18 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 
				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),

	DEF_PD("scif0",		R9A08G045_PD_SCIF0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),

	DEF_PD("scif1",		R9A08G045_PD_SCIF1,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0),

	DEF_PD("scif2",		R9A08G045_PD_SCIF2,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0),

	DEF_PD("scif3",		R9A08G045_PD_SCIF3,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0),

	DEF_PD("scif4",		R9A08G045_PD_SCIF4,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),

	DEF_PD("scif5",		R9A08G045_PD_SCIF5,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),

	DEF_PD("adc",		R9A08G045_PD_ADC,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),

	DEF_PD("vbat",		R9A08G045_PD_VBAT,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),

				GENPD_FLAG_ALWAYS_ON),

drivers/clk/renesas/r9a09g057-cpg.c

+45 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ enum clk_ids { 
	CLK_PLLCLN,

	CLK_PLLDTY,

	CLK_PLLCA55,

	CLK_PLLVDO,



	/* Internal Core Clocks */

	CLK_PLLCM33_DIV16,
@@ -35,7 +36,13 @@ enum clk_ids { 
	CLK_PLLCLN_DIV8,

	CLK_PLLCLN_DIV16,

	CLK_PLLDTY_ACPU,

	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV16,

	CLK_PLLVDO_CRU0,

	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_CRU2,

	CLK_PLLVDO_CRU3,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -49,6 +56,12 @@ static const struct clk_div_table dtable_1_8[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_2_4[] = {

	{0, 2},

	{1, 4},

	{0, 0},

};



static const struct clk_div_table dtable_2_64[] = {

	{0, 2},

	{1, 4},
@@ -69,6 +82,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),

	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),

	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),

	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),



	/* Internal Core Clocks */

	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
@@ -78,7 +92,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),



	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),



	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),

	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),

	DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),

	DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),



	/* Core Clocks */

	DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -133,6 +154,18 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12),

	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13),

	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),

	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),

	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19),

	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20),

	DEF_MOD("cru_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),

	DEF_MOD_NO_PM("cru_1_vclk",		CLK_PLLVDO_CRU1, 13, 6, 6, 22),

	DEF_MOD("cru_1_pclk",			CLK_PLLDTY_DIV16, 13, 7, 6, 23),

	DEF_MOD("cru_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),

	DEF_MOD_NO_PM("cru_2_vclk",		CLK_PLLVDO_CRU2, 13, 9, 6, 25),

	DEF_MOD("cru_2_pclk",			CLK_PLLDTY_DIV16, 13, 10, 6, 26),

	DEF_MOD("cru_3_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),

	DEF_MOD_NO_PM("cru_3_vclk",		CLK_PLLVDO_CRU3, 13, 12, 6, 28),

	DEF_MOD("cru_3_pclk",			CLK_PLLDTY_DIV16, 13, 13, 6, 29),

};



static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -162,6 +195,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */

	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */

	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */

	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */

	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */

	DEF_RST(12, 8, 5, 25),		/* CRU_1_PRESETN */

	DEF_RST(12, 9, 5, 26),		/* CRU_1_ARESETN */

	DEF_RST(12, 10, 5, 27),		/* CRU_1_S_RESETN */

	DEF_RST(12, 11, 5, 28),		/* CRU_2_PRESETN */

	DEF_RST(12, 12, 5, 29),		/* CRU_2_ARESETN */

	DEF_RST(12, 13, 5, 30),		/* CRU_2_S_RESETN */

	DEF_RST(12, 14, 5, 31),		/* CRU_3_PRESETN */

	DEF_RST(12, 15, 6, 0),		/* CRU_3_ARESETN */

	DEF_RST(13, 0, 6, 1),		/* CRU_3_S_RESETN */

};



const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {

drivers/clk/renesas/renesas-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -979,7 +979,7 @@ static void __init cpg_mssr_reserved_exit(struct cpg_mssr_priv *priv) 
static int __init cpg_mssr_reserved_init(struct cpg_mssr_priv *priv,

					 const struct cpg_mssr_info *info)

{

	struct device_node *soc = of_find_node_by_path("/soc");

	struct device_node *soc __free(device_node) = of_find_node_by_path("/soc");

	struct device_node *node;

	uint32_t args[MAX_PHANDLE_ARGS];

	unsigned int *ids = NULL;