Commit 39abdcbd authored by Qiuxu Zhuo's avatar Qiuxu Zhuo Committed by Tony Luck
Browse files

EDAC/skx_common: Extend the maximum number of DRAM chip row bits 



The allowed maximum number of row bits for DRAM chips in the Diamond
Rapids server processor is up to 19. Extend the current maximum row
bits from 18 to 19.

Tested-by: default avatarYi Lai <yi1.lai@intel.com>
Signed-off-by: default avatarQiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20251119134132.2389472-6-qiuxu.zhuo@intel.com
parent 9fc67b11

drivers/edac/skx_common.c

+1 −1
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, 
}



#define numrank(reg)	skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")

#define numrow(reg)	skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")

#define numrow(reg)	skx_get_dimm_attr(reg, 2, 4, 12, 1, 7, "rows")

#define numcol(reg)	skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")



int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,