Commit 39bd5f82 authored by Minda Chen's avatar Minda Chen Committed by Bjorn Helgaas
Browse files

PCI: microchip: Move PLDA functions to pcie-plda-host.c 

Move plda_pcie_setup_window() and plda_pcie_setup_iomems() to
pcie-plda-host.c so they can be shared by all PLDA-based drivers.

Link: https://lore.kernel.org/linux-pci/20240328091835.14797-10-minda.chen@starfivetech.com


Signed-off-by: default avatarMinda Chen <minda.chen@starfivetech.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent ed18db13

MAINTAINERS

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@@ -17224,6 +17224,7 @@ M: Daire McNamara <daire.mcnamara@microchip.com> 
L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml

F:	drivers/pci/controller/plda/pcie-plda-host.c

F:	drivers/pci/controller/plda/pcie-plda.h









PCI DRIVER FOR RENESAS R-CAR

























drivers/pci/controller/plda/Kconfig



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@@ -3,10 +3,14 @@







menu "PLDA-based PCIe controllers"









	depends on PCI



















config PCIE_PLDA_HOST









	bool



















config PCIE_MICROCHIP_HOST









	tristate "Microchip AXI PCIe controller"









	depends on PCI_MSI && OF









	select PCI_HOST_COMMON









	select PCIE_PLDA_HOST









	help









	  Say Y here if you want kernel to support the Microchip AXI PCIe









	  Host Bridge driver.
































drivers/pci/controller/plda/Makefile



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# SPDX-License-Identifier: GPL-2.0









obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o









obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
























drivers/pci/controller/plda/pcie-microchip-host.c



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@@ -838,66 +838,6 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port)







	return mc_allocate_msi_domains(port);









}



















static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,









				   phys_addr_t axi_addr, phys_addr_t pci_addr,









				   size_t size)









{









	u32 atr_sz = ilog2(size) - 1;









	u32 val;



















	if (index == 0)









		val = PCIE_CONFIG_INTERFACE;









	else









		val = PCIE_TX_RX_INTERFACE;



















	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_TRSL_PARAM);



















	val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |









			    ATR_IMPL_ENABLE;









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_SRCADDR_PARAM);



















	val = upper_32_bits(axi_addr);









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_SRC_ADDR);



















	val = lower_32_bits(pci_addr);









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_TRSL_ADDR_LSB);



















	val = upper_32_bits(pci_addr);









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_TRSL_ADDR_UDW);



















	val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);









	val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);









	writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);









	writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);









}



















static int plda_pcie_setup_iomems(struct platform_device *pdev,









				  struct plda_pcie_rp *port)









{









	void __iomem *bridge_base_addr = port->bridge_addr;









	struct pci_host_bridge *bridge = platform_get_drvdata(pdev);









	struct resource_entry *entry;









	u64 pci_addr;









	u32 index = 1;



















	resource_list_for_each_entry(entry, &bridge->windows) {









		if (resource_type(entry->res) == IORESOURCE_MEM) {









			pci_addr = entry->res->start - entry->offset;









			plda_pcie_setup_window(bridge_base_addr, index,









					       entry->res->start, pci_addr,









					       resource_size(entry->res));









			index++;









		}









	}



















	return 0;









}



















static inline void mc_clear_secs(struct mc_pcie *port)









{









	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
































drivers/pci/controller/plda/pcie-plda-host.c
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// SPDX-License-Identifier: GPL-2.0









/*









 * PLDA PCIe XpressRich host controller driver









 *









 * Copyright (C) 2023 Microchip Co. Ltd









 *









 * Author: Daire McNamara <daire.mcnamara@microchip.com>









 */



















#include <linux/pci-ecam.h>



















#include "pcie-plda.h"



















void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,









			    phys_addr_t axi_addr, phys_addr_t pci_addr,









			    size_t size)









{









	u32 atr_sz = ilog2(size) - 1;









	u32 val;



















	if (index == 0)









		val = PCIE_CONFIG_INTERFACE;









	else









		val = PCIE_TX_RX_INTERFACE;



















	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_TRSL_PARAM);



















	val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |









			    ATR_IMPL_ENABLE;









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_SRCADDR_PARAM);



















	val = upper_32_bits(axi_addr);









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_SRC_ADDR);



















	val = lower_32_bits(pci_addr);









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_TRSL_ADDR_LSB);



















	val = upper_32_bits(pci_addr);









	writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +









	       ATR0_AXI4_SLV0_TRSL_ADDR_UDW);



















	val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);









	val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);









	writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);









	writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);









}









EXPORT_SYMBOL_GPL(plda_pcie_setup_window);



















int plda_pcie_setup_iomems(struct platform_device *pdev,









			   struct plda_pcie_rp *port)









{









	void __iomem *bridge_base_addr = port->bridge_addr;









	struct pci_host_bridge *bridge = platform_get_drvdata(pdev);









	struct resource_entry *entry;









	u64 pci_addr;









	u32 index = 1;



















	resource_list_for_each_entry(entry, &bridge->windows) {









		if (resource_type(entry->res) == IORESOURCE_MEM) {









			pci_addr = entry->res->start - entry->offset;









			plda_pcie_setup_window(bridge_base_addr, index,









					       entry->res->start, pci_addr,









					       resource_size(entry->res));









			index++;









		}









	}



















	return 0;









}









EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems);