Commit 39e4d3c2 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Apply underrun on PSR idle workaround 



This patch is applying workaround for underrun on idle PSR HW issue
(Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable
status, DC5/6 enabled disabled and enabled pipes count information made
available.

This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe
enable/disable notification functions as needed.
intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable
notification on PSR capable system.

v2: use intel_dmc interface instead of directly writing dmc register

Bspec: 74151
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-12-jouni.hogander@intel.com
parent 2978eb18

drivers/gpu/drm/i915/display/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -6659,6 +6659,8 @@ static void intel_enable_crtc(struct intel_atomic_state *state, 
		intel_crtc_update_active_timings(pipe_crtc_state, false);

	}



	intel_psr_notify_pipe_change(state, crtc, true);



	display->funcs.display->crtc_enable(state, crtc);



	/* vblanks work again, re-enable pipe CRC. */
@@ -6778,6 +6780,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 
					 intel_crtc_joined_pipe_mask(old_crtc_state))

		intel_crtc_disable_pipe_crc(pipe_crtc);



	intel_psr_notify_pipe_change(state, crtc, false);



	display->funcs.display->crtc_disable(state, crtc);



	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

drivers/gpu/drm/i915/display/intel_display_driver.c

+3 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
#include "intel_plane_initial.h"

#include "intel_pmdemand.h"

#include "intel_pps.h"

#include "intel_psr.h"

#include "intel_quirks.h"

#include "intel_vga.h"

#include "intel_wm.h"
@@ -226,6 +227,8 @@ int intel_display_driver_probe_noirq(struct intel_display *display) 
	if (ret)

		goto cleanup_bios;



	intel_psr_dc5_dc6_wa_init(display);



	/* FIXME: completely on the wrong abstraction layer */

	ret = intel_power_domains_init(display);

	if (ret < 0)

drivers/gpu/drm/i915/display/intel_display_irq.c

+1 −8
Original line number Diff line number Diff line
@@ -1704,14 +1704,7 @@ static void intel_display_vblank_dc_work(struct work_struct *work) 
		container_of(work, typeof(*display), irq.vblank_dc_work);

	int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes);



	/*

	 * NOTE: intel_display_power_set_target_dc_state is used only by PSR

	 * code for DC3CO handling. DC3CO target state is currently disabled in

	 * PSR code. If DC3CO is taken into use we need take that into account

	 * here as well.

	 */

	intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE :

						DC_STATE_EN_UPTO_DC6);

	intel_psr_notify_vblank_enable_disable(display, vblank_wa_num_pipes);

}



int bdw_enable_vblank(struct drm_crtc *_crtc)

drivers/gpu/drm/i915/display/intel_display_power_well.c

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "intel_hotplug.h"

#include "intel_pcode.h"

#include "intel_pps.h"

#include "intel_psr.h"

#include "intel_tc.h"

#include "intel_vga.h"

#include "skl_watermark.h"
@@ -760,6 +761,9 @@ void gen9_set_dc_state(struct intel_display *display, u32 state) 
			     state & ~power_domains->allowed_dc_mask))

		state &= power_domains->allowed_dc_mask;



	if (!power_domains->initializing)

		intel_psr_notify_dc5_dc6(display);



	val = intel_de_read(display, DC_STATE_EN);

	mask = gen9_dc_mask(display);

	drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n",

drivers/gpu/drm/i915/display/intel_psr.c

+49 −40
Original line number Diff line number Diff line
@@ -907,6 +907,18 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 
	return idle_frames;

}



static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	u32 current_dc_state = intel_display_power_get_current_dc_state(display);

	struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe];



	return (current_dc_state != DC_STATE_EN_UPTO_DC5 &&

		current_dc_state != DC_STATE_EN_UPTO_DC6) ||

		intel_dp->psr.active_non_psr_pipes ||

		READ_ONCE(vblank->enabled);

}



static void hsw_activate_psr1(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);
@@ -935,6 +947,14 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) 


	intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder),

		     ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);



	/* Wa_16025596647 */

	if ((DISPLAY_VER(display) == 20 ||

	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

	    is_dc5_dc6_blocked(intel_dp))

		intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

								       intel_dp->psr.pipe,

								       true);

}



static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
@@ -1016,8 +1036,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

	u32 val = EDP_PSR2_ENABLE;

	u32 psr_val = 0;

	u8 idle_frames;



	val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));

	/* Wa_16025596647 */

	if ((DISPLAY_VER(display) == 20 ||

	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

	    is_dc5_dc6_blocked(intel_dp))

		idle_frames = 0;

	else

		idle_frames = psr_compute_idle_frames(intel_dp);

	val |= EDP_PSR2_IDLE_FRAMES(idle_frames);



	if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)

		val |= EDP_SU_TRACK_ENABLE;
@@ -2090,6 +2118,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp) 


		drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));

	} else {

		if (DISPLAY_VER(display) == 20 ||

		    IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

			intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

								       intel_dp->psr.pipe,

								       false);



		val = intel_de_rmw(display,

				   psr_ctl_reg(display, cpu_transcoder),

				   EDP_PSR_ENABLE, 0);
@@ -2302,6 +2336,7 @@ void intel_psr_resume(struct intel_dp *intel_dp) 
bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_encoder *encoder;



	for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) {
@@ -2312,8 +2347,15 @@ bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) 


		intel_dp = enc_to_intel_dp(encoder);



		if (intel_dp_is_edp(intel_dp) &&

		    CAN_PANEL_REPLAY(intel_dp))

		if (!intel_dp_is_edp(intel_dp))

			continue;



		if (CAN_PANEL_REPLAY(intel_dp))

			return true;



		if ((DISPLAY_VER(display) == 20 ||

		     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

		    CAN_PSR(intel_dp))

			return true;

	}
@@ -3642,45 +3684,10 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 
	}

}



/* Wa_16025596647 */

static void psr1_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp,

						  bool dc5_dc6_blocked)

{

	struct intel_display *display = to_intel_display(intel_dp);

	u32 val;



	if (dc5_dc6_blocked)

		val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |

			REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,

				       DMC_EVT_CTL_TYPE_EDGE_0_1) |

			REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,

				       DMC_EVT_CTL_EVENT_ID_VBLANK_A);

	else

		val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,

				     DMC_EVT_CTL_EVENT_ID_FALSE) |

			REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,

				       DMC_EVT_CTL_TYPE_EDGE_0_1);



	intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(intel_dp->psr.pipe),

		       val);

}



/* Wa_16025596647 */

static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	u32 current_dc_state = intel_display_power_get_current_dc_state(display);

	struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe];



	return (current_dc_state != DC_STATE_EN_UPTO_DC5 &&

		current_dc_state != DC_STATE_EN_UPTO_DC6) ||

		intel_dp->psr.active_non_psr_pipes ||

		READ_ONCE(vblank->enabled);

}



/* Wa_16025596647 */

static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	bool dc5_dc6_blocked;



	if (!intel_dp->psr.active)
@@ -3692,7 +3699,9 @@ static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp 
		psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 :

					 psr_compute_idle_frames(intel_dp));

	else

		psr1_apply_underrun_on_idle_wa_locked(intel_dp, dc5_dc6_blocked);

		intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

								       intel_dp->psr.pipe,

								       dc5_dc6_blocked);

}



static void psr_dc5_dc6_wa_work(struct work_struct *work)