Commit 3a17ba65 authored by André Draszik's avatar André Draszik Committed by Lee Jones
Browse files

mfd: sec: Add support for S2MPG11 PMIC via ACPM 



Add support for Samsung's S2MPG11 PMIC, which is a Power Management IC
for mobile applications with buck converters, various LDOs, power
meters, NTC thermistor inputs, and additional GPIO interfaces. It
typically complements an S2MPG10 PMIC in a main/sub configuration as
the sub-PMIC.

Like S2MPG10, communication is not via I2C, but via the Samsung ACPM
firmware.

While at it, we can also switch to asynchronous probe, which helps with
probe performance, as the drivers for s2mpg10 and s2mpg11 can probe in
parallel.

Note: The firmware uses the ACPM channel ID and the Speedy channel ID
to select the PMIC address. Since these are firmware properties, they
can not be retrieved from DT, but instead are deducted from the
compatible for now.

Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20260122-s2mpg1x-regulators-v7-9-3b1f9831fffd@linaro.org


Signed-off-by: default avatarLee Jones <lee@kernel.org>
parent fa72a842

drivers/mfd/sec-acpm.c

+167 −4
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/mfd/samsung/core.h>

#include <linux/mfd/samsung/rtc.h>

#include <linux/mfd/samsung/s2mpg10.h>

#include <linux/mfd/samsung/s2mpg11.h>

#include <linux/mod_devicetable.h>

#include <linux/module.h>

#include <linux/of.h>
@@ -216,6 +217,155 @@ static const struct regmap_config s2mpg10_regmap_config_meter = { 
	.cache_type = REGCACHE_FLAT,

};



static const struct regmap_range s2mpg11_common_registers[] = {

	regmap_reg_range(0x00, 0x02), /* CHIP_ID_S, INT, INT_MASK */

	regmap_reg_range(0x0a, 0x0c), /* Speedy control */

	regmap_reg_range(0x1a, 0x27), /* Debug */

};



static const struct regmap_range s2mpg11_common_ro_registers[] = {

	regmap_reg_range(0x00, 0x01), /* CHIP_ID_S, INT */

	regmap_reg_range(0x25, 0x27), /* Debug */

};



static const struct regmap_range s2mpg11_common_nonvolatile_registers[] = {

	regmap_reg_range(0x00, 0x00), /* CHIP_ID_S */

	regmap_reg_range(0x02, 0x02), /* INT_MASK */

	regmap_reg_range(0x0a, 0x0c), /* Speedy control */

};



static const struct regmap_range s2mpg11_common_precious_registers[] = {

	regmap_reg_range(0x01, 0x01), /* INT */

};



static const struct regmap_access_table s2mpg11_common_wr_table = {

	.yes_ranges = s2mpg11_common_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers),

	.no_ranges = s2mpg11_common_ro_registers,

	.n_no_ranges = ARRAY_SIZE(s2mpg11_common_ro_registers),

};



static const struct regmap_access_table s2mpg11_common_rd_table = {

	.yes_ranges = s2mpg11_common_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers),

};



static const struct regmap_access_table s2mpg11_common_volatile_table = {

	.no_ranges = s2mpg11_common_nonvolatile_registers,

	.n_no_ranges = ARRAY_SIZE(s2mpg11_common_nonvolatile_registers),

};



static const struct regmap_access_table s2mpg11_common_precious_table = {

	.yes_ranges = s2mpg11_common_precious_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_precious_registers),

};



static const struct regmap_config s2mpg11_regmap_config_common = {

	.name = "common",

	.reg_bits = ACPM_ADDR_BITS,

	.val_bits = 8,

	.max_register = S2MPG11_COMMON_SPD_DEBUG4,

	.wr_table = &s2mpg11_common_wr_table,

	.rd_table = &s2mpg11_common_rd_table,

	.volatile_table = &s2mpg11_common_volatile_table,

	.precious_table = &s2mpg11_common_precious_table,

	.num_reg_defaults_raw = S2MPG11_COMMON_SPD_DEBUG4 + 1,

	.cache_type = REGCACHE_FLAT,

};



static const struct regmap_range s2mpg11_pmic_registers[] = {

	regmap_reg_range(0x00, 0x5a), /* All PMIC registers */

	regmap_reg_range(0x5c, 0xb7), /* All PMIC registers */

};



static const struct regmap_range s2mpg11_pmic_ro_registers[] = {

	regmap_reg_range(0x00, 0x05), /* INTx */

	regmap_reg_range(0x0c, 0x0d), /* STATUS OFFSRC */

	regmap_reg_range(0x98, 0x98), /* GPIO input */

};



static const struct regmap_range s2mpg11_pmic_nonvolatile_registers[] = {

	regmap_reg_range(0x06, 0x0b), /* INTxM */

};



static const struct regmap_range s2mpg11_pmic_precious_registers[] = {

	regmap_reg_range(0x00, 0x05), /* INTx */

};



static const struct regmap_access_table s2mpg11_pmic_wr_table = {

	.yes_ranges = s2mpg11_pmic_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers),

	.no_ranges = s2mpg11_pmic_ro_registers,

	.n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_ro_registers),

};



static const struct regmap_access_table s2mpg11_pmic_rd_table = {

	.yes_ranges = s2mpg11_pmic_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers),

};



static const struct regmap_access_table s2mpg11_pmic_volatile_table = {

	.no_ranges = s2mpg11_pmic_nonvolatile_registers,

	.n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_nonvolatile_registers),

};



static const struct regmap_access_table s2mpg11_pmic_precious_table = {

	.yes_ranges = s2mpg11_pmic_precious_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_precious_registers),

};



static const struct regmap_config s2mpg11_regmap_config_pmic = {

	.name = "pmic",

	.reg_bits = ACPM_ADDR_BITS,

	.val_bits = 8,

	.max_register = S2MPG11_PMIC_LDO_SENSE2,

	.wr_table = &s2mpg11_pmic_wr_table,

	.rd_table = &s2mpg11_pmic_rd_table,

	.volatile_table = &s2mpg11_pmic_volatile_table,

	.precious_table = &s2mpg11_pmic_precious_table,

	.num_reg_defaults_raw = S2MPG11_PMIC_LDO_SENSE2 + 1,

	.cache_type = REGCACHE_FLAT,

};



static const struct regmap_range s2mpg11_meter_registers[] = {

	regmap_reg_range(0x00, 0x3e), /* Meter config */

	regmap_reg_range(0x40, 0x8a), /* Meter data */

	regmap_reg_range(0x8d, 0x9c), /* Meter data */

};



static const struct regmap_range s2mpg11_meter_ro_registers[] = {

	regmap_reg_range(0x40, 0x9c), /* Meter data */

};



static const struct regmap_access_table s2mpg11_meter_wr_table = {

	.yes_ranges = s2mpg11_meter_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers),

	.no_ranges = s2mpg11_meter_ro_registers,

	.n_no_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers),

};



static const struct regmap_access_table s2mpg11_meter_rd_table = {

	.yes_ranges = s2mpg11_meter_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers),

};



static const struct regmap_access_table s2mpg11_meter_volatile_table = {

	.yes_ranges = s2mpg11_meter_ro_registers,

	.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers),

};



static const struct regmap_config s2mpg11_regmap_config_meter = {

	.name = "meter",

	.reg_bits = ACPM_ADDR_BITS,

	.val_bits = 8,

	.max_register = S2MPG11_METER_LPF_DATA_NTC7_2,

	.wr_table = &s2mpg11_meter_wr_table,

	.rd_table = &s2mpg11_meter_rd_table,

	.volatile_table = &s2mpg11_meter_volatile_table,

	.num_reg_defaults_raw = S2MPG11_METER_LPF_DATA_NTC7_2 + 1,

	.cache_type = REGCACHE_FLAT,

};



struct sec_pmic_acpm_shared_bus_context {

	const struct acpm_handle *acpm;

	unsigned int acpm_chan_id;
@@ -364,10 +514,12 @@ static int sec_pmic_acpm_probe(struct platform_device *pdev) 
	if (IS_ERR(regmap_pmic))

		return PTR_ERR(regmap_pmic);



	if (pdata->regmap_cfg_rtc) {

		regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC,

						   pdata->regmap_cfg_rtc, true);

		if (IS_ERR(regmap))

			return PTR_ERR(regmap);

	}



	regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_METER,

					   pdata->regmap_cfg_meter, true);
@@ -399,8 +551,18 @@ static const struct sec_pmic_acpm_platform_data s2mpg10_data = { 
	.regmap_cfg_meter = &s2mpg10_regmap_config_meter,

};



static const struct sec_pmic_acpm_platform_data s2mpg11_data = {

	.device_type = S2MPG11,

	.acpm_chan_id = 2,

	.speedy_channel = 1,

	.regmap_cfg_common = &s2mpg11_regmap_config_common,

	.regmap_cfg_pmic = &s2mpg11_regmap_config_pmic,

	.regmap_cfg_meter = &s2mpg11_regmap_config_meter,

};



static const struct of_device_id sec_pmic_acpm_of_match[] = {

	{ .compatible = "samsung,s2mpg10-pmic", .data = &s2mpg10_data, },

	{ .compatible = "samsung,s2mpg11-pmic", .data = &s2mpg11_data, },

	{ },

};

MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match);
@@ -408,6 +570,7 @@ MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match); 
static struct platform_driver sec_pmic_acpm_driver = {

	.driver = {

		.name = "sec-pmic-acpm",

		.probe_type = PROBE_PREFER_ASYNCHRONOUS,

		.pm = pm_sleep_ptr(&sec_pmic_pm_ops),

		.of_match_table = sec_pmic_acpm_of_match,

	},

drivers/mfd/sec-common.c

+16 −1
Original line number Diff line number Diff line
@@ -49,6 +49,12 @@ static const struct mfd_cell s2mpg10_devs[] = { 
	MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"),

};



static const struct mfd_cell s2mpg11_devs[] = {

	MFD_CELL_NAME("s2mpg11-meter"),

	MFD_CELL_NAME("s2mpg11-regulator"),

	MFD_CELL_OF("s2mpg11-gpio", NULL, NULL, 0, 0, "samsung,s2mpg11-gpio"),

};



static const struct resource s2mps11_rtc_resources[] = {

	DEFINE_RES_IRQ_NAMED(S2MPS11_IRQ_RTCA0, "alarm"),

};
@@ -104,8 +110,13 @@ static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) 
	unsigned int val;



	/* For s2mpg1x, the revision is in a different regmap */

	if (sec_pmic->device_type == S2MPG10)

	switch (sec_pmic->device_type) {

	case S2MPG10:

	case S2MPG11:

		return;

	default:

		break;

	}



	/* For each device type, the REG_ID is always the first register */

	if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val))
@@ -211,6 +222,10 @@ int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq, 
		sec_devs = s2mpg10_devs;

		num_sec_devs = ARRAY_SIZE(s2mpg10_devs);

		break;

	case S2MPG11:

		sec_devs = s2mpg11_devs;

		num_sec_devs = ARRAY_SIZE(s2mpg11_devs);

		break;

	case S2MPS11X:

		sec_devs = s2mps11_devs;

		num_sec_devs = ARRAY_SIZE(s2mps11_devs);

drivers/mfd/sec-irq.c

+85 −1
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/mfd/samsung/core.h>

#include <linux/mfd/samsung/irq.h>

#include <linux/mfd/samsung/s2mpg10.h>

#include <linux/mfd/samsung/s2mpg11.h>

#include <linux/mfd/samsung/s2mps11.h>

#include <linux/mfd/samsung/s2mps14.h>

#include <linux/mfd/samsung/s2mpu02.h>
@@ -79,6 +80,64 @@ static const struct regmap_irq s2mpg10_pmic_irqs[] = { 
	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK),

};



static const struct regmap_irq s2mpg11_irqs[] = {

	REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_PMIC, 0, S2MPG11_COMMON_INT_SRC_PMIC),

	/* No documentation or other reference for remaining bits */

	REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)),

};



static const struct regmap_irq s2mpg11_pmic_irqs[] = {

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_MASK),



	REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK),



	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK),



	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK),



	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK),



	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK),

	REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK),

};



static const struct regmap_irq s2mps11_irqs[] = {

	REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),

	REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
@@ -186,7 +245,7 @@ static const struct regmap_irq s5m8767_irqs[] = { 
	REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),

};



/* All S2MPG10 interrupt sources are read-only and don't require clearing */

/* All S2MPG1x interrupt sources are read-only and don't require clearing */

static const struct regmap_irq_chip s2mpg10_irq_chip = {

	.name = "s2mpg10",

	.status_base = S2MPG10_COMMON_INT,
@@ -205,6 +264,25 @@ static const struct regmap_irq_chip s2mpg10_irq_chip_pmic = { 
	.num_irqs = ARRAY_SIZE(s2mpg10_pmic_irqs),

};



static const struct regmap_irq_chip s2mpg11_irq_chip = {

	.name = "s2mpg11",

	.status_base = S2MPG11_COMMON_INT,

	.mask_base = S2MPG11_COMMON_INT_MASK,

	.num_regs = 1,

	.irqs = s2mpg11_irqs,

	.num_irqs = ARRAY_SIZE(s2mpg11_irqs),

};



static const struct regmap_irq_chip s2mpg11_irq_chip_pmic = {

	.name = "s2mpg11-pmic",

	.domain_suffix = "pmic",

	.status_base = S2MPG11_PMIC_INT1,

	.mask_base = S2MPG11_PMIC_INT1M,

	.num_regs = 6,

	.irqs = s2mpg11_pmic_irqs,

	.num_irqs = ARRAY_SIZE(s2mpg11_pmic_irqs),

};



static const struct regmap_irq_chip s2mps11_irq_chip = {

	.name = "s2mps11",

	.irqs = s2mps11_irqs,
@@ -303,6 +381,11 @@ static struct regmap_irq_chip_data *sec_irq_init_s2mpg1x(struct sec_pmic_dev *se 
		chained_irq_chip = &s2mpg10_irq_chip_pmic;

		chained_pirq = S2MPG10_COMMON_IRQ_PMIC;

		break;

	case S2MPG11:

		irq_chip = &s2mpg11_irq_chip;

		chained_irq_chip = &s2mpg11_irq_chip_pmic;

		chained_pirq = S2MPG11_COMMON_IRQ_PMIC;

		break;

	default:

		return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n",

					 sec_pmic->device_type);
@@ -338,6 +421,7 @@ struct regmap_irq_chip_data *sec_irq_init(struct sec_pmic_dev *sec_pmic) 
		sec_irq_chip = &s2mps14_irq_chip;

		break;

	case S2MPG10:

	case S2MPG11:

		return sec_irq_init_s2mpg1x(sec_pmic);

	case S2MPS11X:

		sec_irq_chip = &s2mps11_irq_chip;

include/linux/mfd/samsung/core.h

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ enum sec_device_type { 
	S2DOS05,

	S2MPA01,

	S2MPG10,

	S2MPG11,

	S2MPS11X,

	S2MPS13X,

	S2MPS14X,

include/linux/mfd/samsung/irq.h

+105 −0
Original line number Diff line number Diff line
@@ -166,6 +166,111 @@ enum s2mpg10_irq { 
	S2MPG10_IRQ_NR,

};



enum s2mpg11_common_irq {

	/* Top-level (common) block */

	S2MPG11_COMMON_IRQ_PMIC,

	S2MPG11_COMMON_IRQ_UNUSED,

};



enum s2mpg11_irq {

	/* PMIC */

	S2MPG11_IRQ_PWRONF,

	S2MPG11_IRQ_PWRONR,

	S2MPG11_IRQ_PIF_TIMEOUT_MIF,

	S2MPG11_IRQ_PIF_TIMEOUTS,

	S2MPG11_IRQ_WTSR,

	S2MPG11_IRQ_SPD_ABNORMAL_STOP,

	S2MPG11_IRQ_SPD_PARITY_ERR,

#define S2MPG11_IRQ_PWRONF_MASK			BIT(0)

#define S2MPG11_IRQ_PWRONR_MASK			BIT(1)

#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK	BIT(3)

#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK		BIT(4)

#define S2MPG11_IRQ_WTSR_MASK			BIT(5)

#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK	BIT(6)

#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK		BIT(7)



	S2MPG11_IRQ_140C,

	S2MPG11_IRQ_120C,

	S2MPG11_IRQ_TSD,

	S2MPG11_IRQ_WRST,

	S2MPG11_IRQ_NTC_CYCLE_DONE,

	S2MPG11_IRQ_PMETER_OVERF,

#define S2MPG11_IRQ_INT140C_MASK	BIT(0)

#define S2MPG11_IRQ_INT120C_MASK	BIT(1)

#define S2MPG11_IRQ_TSD_MASK		BIT(2)

#define S2MPG11_IRQ_WRST_MASK		BIT(5)

#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK	BIT(6)

#define S2MPG11_IRQ_PMETER_OVERF_MASK	BIT(7)



	S2MPG11_IRQ_OCP_B1S,

	S2MPG11_IRQ_OCP_B2S,

	S2MPG11_IRQ_OCP_B3S,

	S2MPG11_IRQ_OCP_B4S,

	S2MPG11_IRQ_OCP_B5S,

	S2MPG11_IRQ_OCP_B6S,

	S2MPG11_IRQ_OCP_B7S,

	S2MPG11_IRQ_OCP_B8S,

#define S2MPG11_IRQ_OCP_B1S_MASK	BIT(0)

#define S2MPG11_IRQ_OCP_B2S_MASK	BIT(1)

#define S2MPG11_IRQ_OCP_B3S_MASK	BIT(2)

#define S2MPG11_IRQ_OCP_B4S_MASK	BIT(3)

#define S2MPG11_IRQ_OCP_B5S_MASK	BIT(4)

#define S2MPG11_IRQ_OCP_B6S_MASK	BIT(5)

#define S2MPG11_IRQ_OCP_B7S_MASK	BIT(6)

#define S2MPG11_IRQ_OCP_B8S_MASK	BIT(7)



	S2MPG11_IRQ_OCP_B9S,

	S2MPG11_IRQ_OCP_B10S,

	S2MPG11_IRQ_OCP_BDS,

	S2MPG11_IRQ_OCP_BAS,

	S2MPG11_IRQ_OCP_BBS,

	S2MPG11_IRQ_WLWP_ACC,

	S2MPG11_IRQ_SPD_SRP_PKT_RST,

#define S2MPG11_IRQ_OCP_B9S_MASK		BIT(0)

#define S2MPG11_IRQ_OCP_B10S_MASK		BIT(1)

#define S2MPG11_IRQ_OCP_BDS_MASK		BIT(2)

#define S2MPG11_IRQ_OCP_BAS_MASK		BIT(3)

#define S2MPG11_IRQ_OCP_BBS_MASK		BIT(4)

#define S2MPG11_IRQ_WLWP_ACC_MASK		BIT(5)

#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK	BIT(7)



	S2MPG11_IRQ_PWR_WARN_CH0,

	S2MPG11_IRQ_PWR_WARN_CH1,

	S2MPG11_IRQ_PWR_WARN_CH2,

	S2MPG11_IRQ_PWR_WARN_CH3,

	S2MPG11_IRQ_PWR_WARN_CH4,

	S2MPG11_IRQ_PWR_WARN_CH5,

	S2MPG11_IRQ_PWR_WARN_CH6,

	S2MPG11_IRQ_PWR_WARN_CH7,

#define S2MPG11_IRQ_PWR_WARN_CH0_MASK	BIT(0)

#define S2MPG11_IRQ_PWR_WARN_CH1_MASK	BIT(1)

#define S2MPG11_IRQ_PWR_WARN_CH2_MASK	BIT(2)

#define S2MPG11_IRQ_PWR_WARN_CH3_MASK	BIT(3)

#define S2MPG11_IRQ_PWR_WARN_CH4_MASK	BIT(4)

#define S2MPG11_IRQ_PWR_WARN_CH5_MASK	BIT(5)

#define S2MPG11_IRQ_PWR_WARN_CH6_MASK	BIT(6)

#define S2MPG11_IRQ_PWR_WARN_CH7_MASK	BIT(7)



	S2MPG11_IRQ_NTC_WARN_CH0,

	S2MPG11_IRQ_NTC_WARN_CH1,

	S2MPG11_IRQ_NTC_WARN_CH2,

	S2MPG11_IRQ_NTC_WARN_CH3,

	S2MPG11_IRQ_NTC_WARN_CH4,

	S2MPG11_IRQ_NTC_WARN_CH5,

	S2MPG11_IRQ_NTC_WARN_CH6,

	S2MPG11_IRQ_NTC_WARN_CH7,

#define S2MPG11_IRQ_NTC_WARN_CH0_MASK	BIT(0)

#define S2MPG11_IRQ_NTC_WARN_CH1_MASK	BIT(1)

#define S2MPG11_IRQ_NTC_WARN_CH2_MASK	BIT(2)

#define S2MPG11_IRQ_NTC_WARN_CH3_MASK	BIT(3)

#define S2MPG11_IRQ_NTC_WARN_CH4_MASK	BIT(4)

#define S2MPG11_IRQ_NTC_WARN_CH5_MASK	BIT(5)

#define S2MPG11_IRQ_NTC_WARN_CH6_MASK	BIT(6)

#define S2MPG11_IRQ_NTC_WARN_CH7_MASK	BIT(7)



	S2MPG11_IRQ_NR,

};



enum s2mps11_irq {

	S2MPS11_IRQ_PWRONF,

	S2MPS11_IRQ_PWRONR,